PRUSSv2 Memory Map

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Local Data Memory Map

The following memory mappings may only be used from within the PRUSS.

Start Address PRU0 PRU1 Description
0x0000_0000 Data 8KB RAM 0 Data 8KB RAM 1 8KB data RAM belonging to PRU0
0x0000_2000 Data 8KB RAM 1 Data 8KB RAM 0 8KB data RAM belonging to PRU1
0x0001_0000 Data 12KB RAM 2 (Shared) Data 12KB RAM 2 (Shared) 12KB data RAM shared between both PRUs
0x0002_0000 INTC INTC  ?
0x0002_2000 PRU0 Control Registers PRU0 Control Registers  ?
0x0002_2400 Reserved Reserved -
0x0002_4000 PRU1 Control Registers PRU1 Control Registers  ?
0x0002_4400 Reserved Reserved -
0x0002_6000 CFG CFG  ?
0x0002_8000 UART 0 UART 0 PRUSS dedicated UART Controller (Universal Asynchronous Receive/Transmit Controller)
0x0002_A000 Reserved Reserved -
0x0002_C000 Reserved Reserved -
0x0002_E000 IEP IEP  ?
0x0003_0000 eCAP 0 eCAP 0  ?
0x0003_2000 MII_RT_CFG MII_RT_CFG  ?
0x0003_2400 MII_MDIO MII_MDIO  ?
0x0003_4000 Reserved Reserved -
0x0003_8000 Reserved Reserved -
0x0004_0000 Reserved Reserved -
0x0008_0000 System OCP_HP0 System OCP_HP1 Address Offset of the Interface/OCP Master Port used to access the host memory map

Global Memory Map

The following memory mappings may be used either from the host ARM Cortex-A8 CPU or from within the PRUSS.

It is recommended to use local mappings from within the PRUSS however, as access times will be faster.

Offset Address PRUSS
0x0000_0000 Data 8KB RAM 0
0x0000_2000 Data 8KB RAM 1
0x0001_0000 Data 12KB RAM 2 (Shared)
0x0002_0000 INTC
0x0002_2000 PRU0 Control
0x0002_2400 PRU0 Debug
0x0002_4000 PRU1 Control
0x0002_4400 PRU1 Debug
0x0002_6000 CFG
0x0002_8000 UART 0
0x0002_A000 Reserved
0x0002_C000 Reserved
0x0002_E000 IEP
0x0003_0000 eCAP 0
0x0003_2000 MII_RT_CFG
0x0003_2400 MII_MDIO
0x0003_4000 PRU0 8KB IRAM
0x0003_8000 PRU1 8KB IRAM
0x0004_0000 Reserved

CFG Register Map

The PRUSS CFG block contains registers for control and status of power management, memory parity and enhanced PRU GP port functions.

Any register offset addresses not listed below should be considered reserved and should not be modified.

PRUSS_CFG Register

Offset (Hexadecimal Bytes) Name Description
0h REVID The Revision Register, contains the ID and revision information.
4h SYSCFG The System Configuration Register, defines the power IDLE and STANDBY modes.
8h GPCFG0 The General Purpose Configuration 0 Register, defines the GPI/O configuration for PRU0.
Ch GPCFG1 The General Purpose Configuration 0 Register, defines the GPI/O configuration for PRU1.
10h CGR The Clock Gating Register, controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x01.
14h ISRP The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRUSS memory parity events. The raw status is set even if the event is not enabled.
18h ISP The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced.
18h ISP The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced.
1Ch IESP The IRQ Enable Set Parity Register enables the IRQ PRUSS memory parity events.
20h IECP The IRQ Enable Clear Parity Register disables the IRQ PRUSS memory parity events.
24h SCRP SCR Priority Register defines the priority of some of the elements in the SCR. Lower numbers indicate higher priority level.
28h PMAO The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x00000.
2Ch MII_RT The MII_RT Event Enable Register enables Ethercat (or MII_RT) mode events to the PRUSS INTC.
30h IEPCLK The IEP Clock Source Register defines the source of the IEP clock.
34h SPP The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality.
40h PIN_MX The Pin Mux Select Register defines the state of the PRUSS internal pinmuxing.