http://elinux.org/api.php?action=feedcontributions&user=Richarsm&feedformat=atom 2013-05-18T06:22:30Z User contributions MediaWiki 1.21alpha http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-16T23:45:33Z

<p>Richarsm: /* Resources */ typo</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> Include the uio_pruss kernel driver by using '''modprobe uio_pruss''' or the steps outlined above, if that does not work.<br /> Then in a project include the header files for the am335x_pru_package.<br /> <br /> #define PRU_NUM0 0<br /> // Driver header file<br /> #include &lt;prussdrv.h&gt;<br /> #include &lt;pruss_intc_mapping.h&gt; <br /> <br /> /* Then, initialize the interrupt controller data */<br /> tpruss_intc_initdata pruss_intc_initdata = PRUSS_INTC_INITDATA;<br /> /* Initialize the PRU */<br /> prussdrv_init ();<br /> /* Get the interrupt initialized */<br /> prussdrv_pruintc_init(&amp;pruss_intc_initdata)<br /> <br /> /* Execute example on PRU0 where first argument is the PRU# and second is the assembly to execute*/<br /> prussdrv_exec_program (PRU_NUM0, &quot;./example.bin&quot;);<br /> <br /> /* Wait until PRU0 sends the interrupt*/<br /> prussdrv_pru_wait_event (PRU_EVTOUT_0);<br /> /* Clear the interrupt*/<br /> prussdrv_pru_clear_event (PRU0_ARM_INTERRUPT);<br /> <br /> The PRU (in this case 0) will have the following in the example.bin file to trigger the interrupt:<br /> #define PRU0_ARM_INTERRUPT 19<br /> MOV r31.b0, PRU0_ARM_INTERRUPT+16<br /> <br /> Register 31 allows for control of the INTC for the PRU.<br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note1)&lt;/span&gt;<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note2)&lt;/span&gt;<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> &lt;pre style=&quot;color: red&quot;&gt;<br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> &lt;/pre&gt;<br /> <br /> == Assembly ==<br /> The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI]. <br /> === Four instruction classes ===<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> === Instruction Syntax ===<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r4, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> * A userspace [https://docs.google.com/file/d/0B80aJokrBccAV1paMTU0bjM1OXc/edit?usp=sharing debugging utility] with credit to PRU_EVTOUT_2 from the #beagle IRC channel.<br /> * ncurses based debugger work has started at [https://github.com/wz2b/prude here].<br /> * For using the Open Core Protocol to [http://nomel.org/post/30006622413/beaglebone-tutorial-accessing-main-memory-from-the-pru access external memory] from the PRU.<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]<br /> <br /> [[Category:ECE497 | PRU]]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-16T23:45:07Z

<p>Richarsm: /* Resources */ Added link to nomel.org for OCP</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> Include the uio_pruss kernel driver by using '''modprobe uio_pruss''' or the steps outlined above, if that does not work.<br /> Then in a project include the header files for the am335x_pru_package.<br /> <br /> #define PRU_NUM0 0<br /> // Driver header file<br /> #include &lt;prussdrv.h&gt;<br /> #include &lt;pruss_intc_mapping.h&gt; <br /> <br /> /* Then, initialize the interrupt controller data */<br /> tpruss_intc_initdata pruss_intc_initdata = PRUSS_INTC_INITDATA;<br /> /* Initialize the PRU */<br /> prussdrv_init ();<br /> /* Get the interrupt initialized */<br /> prussdrv_pruintc_init(&amp;pruss_intc_initdata)<br /> <br /> /* Execute example on PRU0 where first argument is the PRU# and second is the assembly to execute*/<br /> prussdrv_exec_program (PRU_NUM0, &quot;./example.bin&quot;);<br /> <br /> /* Wait until PRU0 sends the interrupt*/<br /> prussdrv_pru_wait_event (PRU_EVTOUT_0);<br /> /* Clear the interrupt*/<br /> prussdrv_pru_clear_event (PRU0_ARM_INTERRUPT);<br /> <br /> The PRU (in this case 0) will have the following in the example.bin file to trigger the interrupt:<br /> #define PRU0_ARM_INTERRUPT 19<br /> MOV r31.b0, PRU0_ARM_INTERRUPT+16<br /> <br /> Register 31 allows for control of the INTC for the PRU.<br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note1)&lt;/span&gt;<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note2)&lt;/span&gt;<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> &lt;pre style=&quot;color: red&quot;&gt;<br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> &lt;/pre&gt;<br /> <br /> == Assembly ==<br /> The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI]. <br /> === Four instruction classes ===<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> === Instruction Syntax ===<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r4, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> * A userspace [https://docs.google.com/file/d/0B80aJokrBccAV1paMTU0bjM1OXc/edit?usp=sharing debugging utility] with credit to PRU_EVTOUT_2 from the #beagle IRC channel.<br /> * ncurses based debugger work has started at [https://github.com/wz2b/prude here].<br /> * For using the Open Connect Protocol to [http://nomel.org/post/30006622413/beaglebone-tutorial-accessing-main-memory-from-the-pru access external memory] from the PRU.<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]<br /> <br /> [[Category:ECE497 | PRU]]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-16T15:49:51Z

<p>Richarsm: /* PRU to Host (PRU to ARM Cortex-A8) */</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> Include the uio_pruss kernel driver by using '''modprobe uio_pruss''' or the steps outlined above, if that does not work.<br /> Then in a project include the header files for the am335x_pru_package.<br /> <br /> #define PRU_NUM0 0<br /> // Driver header file<br /> #include &lt;prussdrv.h&gt;<br /> #include &lt;pruss_intc_mapping.h&gt; <br /> <br /> /* Then, initialize the interrupt controller data */<br /> tpruss_intc_initdata pruss_intc_initdata = PRUSS_INTC_INITDATA;<br /> /* Initialize the PRU */<br /> prussdrv_init ();<br /> /* Get the interrupt initialized */<br /> prussdrv_pruintc_init(&amp;pruss_intc_initdata)<br /> <br /> /* Execute example on PRU0 where first argument is the PRU# and second is the assembly to execute*/<br /> prussdrv_exec_program (PRU_NUM0, &quot;./example.bin&quot;);<br /> <br /> /* Wait until PRU0 sends the interrupt*/<br /> prussdrv_pru_wait_event (PRU_EVTOUT_0);<br /> /* Clear the interrupt*/<br /> prussdrv_pru_clear_event (PRU0_ARM_INTERRUPT);<br /> <br /> The PRU (in this case 0) will have the following in the example.bin file to trigger the interrupt:<br /> #define PRU0_ARM_INTERRUPT 19<br /> MOV r31.b0, PRU0_ARM_INTERRUPT+16<br /> <br /> Register 31 allows for control of the INTC for the PRU.<br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note1)&lt;/span&gt;<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note2)&lt;/span&gt;<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> &lt;pre style=&quot;color: red&quot;&gt;<br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> &lt;/pre&gt;<br /> <br /> == Assembly ==<br /> The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI]. <br /> === Four instruction classes ===<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> === Instruction Syntax ===<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r4, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> * A userspace [https://docs.google.com/file/d/0B80aJokrBccAV1paMTU0bjM1OXc/edit?usp=sharing debugging utility] with credit to PRU_EVTOUT_2 from the #beagle IRC channel.<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]<br /> <br /> [[Category:ECE497 | PRU]]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-16T15:48:05Z

<p>Richarsm: PRU to Host (PRU to ARM Cortex-A8) Added basic interrupt control from the PRU to the ARM processors</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> Include the uio_pruss kernel driver by using '''modprobe uio_pruss''' or the steps outlined above, if that does not work.<br /> Then in a project include the header files for the am335x_pru_package.<br /> <br /> #define PRU_NUM0 0<br /> <br /> /* Then, initialize the interrupt controller data */<br /> tpruss_intc_initdata pruss_intc_initdata = PRUSS_INTC_INITDATA;<br /> /* Initialize the PRU */<br /> prussdrv_init ();<br /> /* Get the interrupt initialized */<br /> prussdrv_pruintc_init(&amp;pruss_intc_initdata)<br /> <br /> /* Execute example on PRU0 where first argument is the PRU# and second is the assembly to execute*/<br /> prussdrv_exec_program (PRU_NUM0, &quot;./example.bin&quot;);<br /> <br /> /* Wait until PRU0 sends the interrupt*/<br /> prussdrv_pru_wait_event (PRU_EVTOUT_0);<br /> /* Clear the interrupt*/<br /> prussdrv_pru_clear_event (PRU0_ARM_INTERRUPT);<br /> <br /> The PRU (in this case 0) will have the following in the example.bin file to trigger the interrupt:<br /> #define PRU0_ARM_INTERRUPT 19<br /> MOV r31.b0, PRU0_ARM_INTERRUPT+16<br /> <br /> Register 31 allows for control of the INTC for the PRU.<br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note1)&lt;/span&gt;<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note2)&lt;/span&gt;<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> &lt;pre style=&quot;color: red&quot;&gt;<br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> &lt;/pre&gt;<br /> <br /> == Assembly ==<br /> The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI]. <br /> === Four instruction classes ===<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> === Instruction Syntax ===<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r4, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> * A userspace [https://docs.google.com/file/d/0B80aJokrBccAV1paMTU0bjM1OXc/edit?usp=sharing debugging utility] with credit to PRU_EVTOUT_2 from the #beagle IRC channel.<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]<br /> <br /> [[Category:ECE497 | PRU]]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-14T04:46:07Z

<p>Richarsm: /* Resources */ Added link to debugger</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note1)&lt;/span&gt;<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |&lt;span style=&quot;color: red&quot;&gt;(*note2)&lt;/span&gt;<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> &lt;pre style=&quot;color: red&quot;&gt;<br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> &lt;/pre&gt;<br /> <br /> == Assembly ==<br /> The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI]. <br /> === Four instruction classes ===<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> === Instruction Syntax ===<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r4, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> * A userspace [https://docs.google.com/file/d/0B80aJokrBccAV1paMTU0bjM1OXc/edit?usp=sharing debugging utility] with credit to PRU_EVTOUT_2 from the #beagle IRC channel.<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]<br /> <br /> [[Category:ECE497 | PRU]]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T19:58:04Z

<p>Richarsm: Added category for ECE497</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Assembly ==<br /> The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI]. <br /> === Four instruction classes ===<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> === Instruction Syntax ===<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r4, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]<br /> <br /> [[Category:ECE497 | PRU]]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T19:53:05Z

<p>Richarsm: Added assembly information</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Assembly ==<br /> The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI]. <br /> === Four instruction classes ===<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> === Instruction Syntax ===<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r4, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T19:42:28Z

<p>Richarsm: /* Communication */ Added a link to the uio_pruss discussion</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T19:36:51Z

<p>Richarsm: /* Available PRU Resources */</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T19:36:38Z

<p>Richarsm: /* Available PRU Resources */ Added hardware layout image</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T19:35:11Z

<p>Richarsm: /* Communication */ fixed link error</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T19:34:42Z

<p>Richarsm: fixed link error</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c | example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]</div>

Richarsm http://elinux.org/Ti_AM33XX_PRUSSv2 2013-05-13T15:12:31Z

<p>Richarsm: fixed Mhz capitalization and idiosyncrasy with access to external memory</p> <hr /> <div>The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.<br /> These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.<br /> <br /> PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.<br /> <br /> ====This is a Work In Progress====<br /> <br /> == Available PRU Resources ==<br /> [[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]<br /> <br /> === Per PRU ===<br /> ; 8KB program memory<br /> : Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.<br /> <br /> ; Enhanced GPIO (EGPIO)<br /> : High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.<br /> :; PRU0<br /> :: ''pr1_pru_0_pru_r30[15:0]'' (PRU0 Register R30 Outputs)<br /> :: ''pr1_pru_0_pru_r31[16:0]'' (PRU0 Register R31 Inputs)<br /> :; PRU1<br /> :: ''pr1_pru_1_pru_r30[15:0]'' (PRU1 Register R30 Outputs)<br /> :: ''pr1_pru_1_pru_r31[16:0]'' (PRU1 Register R31 Inputs)<br /> :; Hardware capture modes<br /> :: Serial 28-bit shift in and out.<br /> :: Parallel 16-bit capture on clock.<br /> :: [http://en.wikipedia.org/wiki/Media_Independent_Interface| MII] standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).<br /> <br /> ; A 32-bit multiply and accumulate unit (MAC)<br /> : Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).<br /> <br /> ; 8KB data memory<br /> : Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.<br /> : One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.<br /> <br /> ; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port<br /> : Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.<br /> <br /> === Shared Between PRUs ===<br /> ; Scratch pad<br /> : 3 banks of 30 32-bit registers (total 90 32-bit registers).<br /> : Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.<br /> <br /> ; 12KB data memory<br /> : Accessed over the 32-but bus, not single-cycle.<br /> <br /> === Local Peripherals ===<br /> Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.<br /> <br /> Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.<br /> <br /> ; Enhanced Capture Model (eCAP)<br /> : <br /> <br /> ; Industrial Ethernet Peripheral (IEP)<br /> <br /> ; Universal Asynchronous Receiver/Transmitter (UART0)<br /> : Used to perform serial data transmission to the TL16C550 industry standard.<br /> : 16-bit FIFO receive and transmit buffers + per byte error status.<br /> : Can generate Interrupt requests for the PRUSS Interrupt Controller.<br /> : Can generate DMA requests for the EDMA SoC DMA controller.<br /> : Maximum transmission speed of 192MHz (192Mbps - 24MB/s).<br /> <br /> == Communication ==<br /> Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.<br /> <br /> The following lists will expose all possible communication approaches for each likely scenario.<br /> <br /> For communication via interrupts, please first read the section on the [[PRUSSv2 Interrupt Controller]].<br /> <br /> [[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]<br /> <br /> The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c|example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace.<br /> <br /> === PRU to Host (PRU to ARM Cortex-A8) ===<br /> <br /> <br /> <br /> <br /> === Host to PRU (ARM Cortex-A8 to PRU) ===<br /> ==== Interrupts ====<br /> Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.<br /> By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.<br /> <br /> To configure <br /> <br /> <br /> === PRU to external peripherals ===<br /> === External peripherals to PRU ===<br /> === PRU to internal peripherals ===<br /> === Internal peripherals to PRU ===<br /> <br /> == Loading a PRU Program ==<br /> <br /> ==Beaglebone PRU connections and modes==<br /> <br /> {| border=&quot;1&quot; class=&quot;wikitable&quot;<br /> |-<br /> |'''PRU #'''<br /> |'''R30(input) bit'''<br /> |'''Pinmux Mode'''<br /> |'''R31(output) bit'''<br /> |'''Pinmux Mode'''<br /> |'''BB Header'''<br /> |'''BB Pin Name'''<br /> |'''ZCZ BallName'''<br /> |'''Offset Reg'''<br /> |'''DT Offset'''<br /> |'''Input Mode'''<br /> |'''Output Mode'''<br /> |-<br /> |0<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P9_31<br /> |SPI1_SCLK<br /> |mcasp0_aclkx<br /> |990h<br /> |0x190<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P9_31<br /> |SPI1_D0<br /> |mcasp0_fsx<br /> |994h<br /> |0x194<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P9_30<br /> |SPI1_D1<br /> |mcasp0_axr0<br /> |998h<br /> |0x198<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P9_28<br /> |SPI1_CS0<br /> |mcasp0_ahclkr<br /> |99Ch<br /> |0x19C<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P9_42<br /> |(*see note1 below)<br /> |mcasp0_aclkr<br /> |9A0h<br /> |0x1A0<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P9_27<br /> |GPIO3_19<br /> |mcasp0_fsr<br /> |9A4h<br /> |0x1A4<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P9_41<br /> |(*see note2 below)<br /> |mcasp0_axr1<br /> |9A8h<br /> |0x1A8<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P9_25<br /> |GPIO3_21<br /> |mcasp0_ahclkx<br /> |9ACh<br /> |0x1AC<br /> |0x06<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |14<br /> |Mode_6<br /> |P8_12<br /> |GPIO1_12<br /> |gpmc_ad12<br /> |830h<br /> |0x030<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |N/A<br /> |<br /> |15<br /> |Mode_6<br /> |P8_11<br /> |GPIO1_13<br /> |gpmc_ad9<br /> |824h<br /> |0x024<br /> |NA<br /> |0x25<br /> |-<br /> |0<br /> |14<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_16<br /> |GPIO1_14<br /> |gpmc_ad14<br /> |838h<br /> |0x038<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |15<br /> |Mode_6<br /> |N/A<br /> |<br /> |P8_15<br /> |GPIO1_15<br /> |gpmc_ad15<br /> |83Ch<br /> |0x03C<br /> |0x06<br /> |NA<br /> |-<br /> |0<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_24<br /> |UART1_TXD<br /> |uart1_txd<br /> |984h<br /> |0x184<br /> |0x06<br /> |NA<br /> |-<br /> |1<br /> |0<br /> |Mode_6<br /> |0<br /> |Mode_5<br /> |P8_45<br /> |GPIO2_6<br /> |lcd_data0<br /> |8A0h<br /> |0x0A0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |1<br /> |Mode_6<br /> |1<br /> |Mode_5<br /> |P8_46<br /> |GPIO2_7<br /> |lcd_data1<br /> |8A4h<br /> |0x0A4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |2<br /> |Mode_6<br /> |2<br /> |Mode_5<br /> |P8_43<br /> |GPIO2_8<br /> |lcd_data2<br /> |8A8h<br /> |0x0A8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |3<br /> |Mode_6<br /> |3<br /> |Mode_5<br /> |P8_44<br /> |GPIO2_9<br /> |lcd_data3<br /> |8ACh<br /> |0x0AC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |4<br /> |Mode_6<br /> |4<br /> |Mode_5<br /> |P8_41<br /> |GPIO2_10<br /> |lcd_data4<br /> |8B0h<br /> |0x0B0<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |5<br /> |Mode_6<br /> |5<br /> |Mode_5<br /> |P8_42<br /> |GPIO2_11<br /> |lcd_data5<br /> |8B4h<br /> |0x0B4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |6<br /> |Mode_6<br /> |6<br /> |Mode_5<br /> |P8_39<br /> |GPIO2_12<br /> |lcd_data6<br /> |8B8h<br /> |0x0B8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |7<br /> |Mode_6<br /> |7<br /> |Mode_5<br /> |P8_40<br /> |GPIO2_13<br /> |lcd_data7<br /> |8BCh<br /> |0x0BC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |8<br /> |Mode_6<br /> |8<br /> |Mode_5<br /> |P8_27<br /> |GPIO2_22<br /> |lcd_vsync<br /> |8E0h<br /> |0x0EO<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |9<br /> |Mode_6<br /> |9<br /> |Mode_5<br /> |P8_29<br /> |GPIO2_23<br /> |lcd_hsync<br /> |8E4h<br /> |0x0E4<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |10<br /> |Mode_6<br /> |10<br /> |Mode_5<br /> |P8_28<br /> |GPIO2_24<br /> |lcd_pclk<br /> |8E8h<br /> |0x0E8<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |11<br /> |Mode_6<br /> |11<br /> |Mode_5<br /> |P8_30<br /> |GPIO2_25<br /> |lcd_ac_bias_en<br /> |8ECh<br /> |0x0EC<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |12<br /> |Mode_6<br /> |12<br /> |Mode_5<br /> |P8_21<br /> |GPIO1_30<br /> |gpmc_csn1<br /> |880h<br /> |0x080<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |13<br /> |Mode_6<br /> |13<br /> |Mode_5<br /> |P8_20<br /> |GPIO1_31<br /> |gpmc_csn2<br /> |884h<br /> |0x084<br /> |0x06<br /> |0x25<br /> |-<br /> |1<br /> |16<br /> |Mode_6<br /> |N/A<br /> |<br /> |P9_26<br /> |UART1_RXD<br /> |uart1_rxd<br /> |980h<br /> |0x180<br /> |0x06<br /> |NA<br /> |-<br /> |}<br /> <br /> *Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.<br /> <br /> *Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.<br /> <br /> == Resources ==<br /> * [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]<br /> * [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]<br /> The documentation on the subsystem is [[media:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.<br /> <br /> * [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]<br /> <br /> == Examples ==<br /> <br /> * [[BeagleBone_6502_RemoteProc_cape]]<br /> * [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]<br /> * [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-25T16:31:36Z

<p>Richarsm: /* Example Assembly */</p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> Data Sheet is located at http://www.ti.com/lit/pdf/spruh73<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.<br /> <br /> Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide<br /> <br /> === Instruction Set ===<br /> Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)<br /> <br /> ==== Four instruction classes ====<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> ==== Instruction Syntax ====<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r3, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3<br /> <br /> ==== Example Assembly ====<br /> &lt;pre&gt;<br /> ;INTC_SIR_IRQ/INTC_SIR_FIQ register address<br /> INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044<br /> ; ACTIVEIRQ bit field mask to get only the bit field<br /> ACTIVEIRQ_MASK .equ 0x7F<br /> _IRQ_ISR/_FIQ_ISR:<br /> ; Save the critical context<br /> STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register<br /> MRS R11, SPSR ; Save the SPSR into R11<br /> ; Get the number of the highest priority active IRQ/FIQ<br /> LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR<br /> LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register<br /> AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number<br /> ; Jump to relevant subroutine handler<br /> LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8<br /> NOP ; To index the table by the PC<br /> ; Table of handler start addresses<br /> .word IRQ0handler ;For IRQ0 of BANK0<br /> .word IRQ1handler<br /> .word IRQ2handler<br /> &lt;/pre&gt;</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-25T16:30:30Z

<p>Richarsm: /* Example Assembly */</p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> Data Sheet is located at http://www.ti.com/lit/pdf/spruh73<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.<br /> <br /> Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide<br /> <br /> === Instruction Set ===<br /> Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)<br /> <br /> ==== Four instruction classes ====<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> ==== Instruction Syntax ====<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r3, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3<br /> <br /> ==== Example Assembly ====<br /> &lt;nowiki&gt;<br /> ;INTC_SIR_IRQ/INTC_SIR_FIQ register address<br /> INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044<br /> ; ACTIVEIRQ bit field mask to get only the bit field<br /> ACTIVEIRQ_MASK .equ 0x7F<br /> _IRQ_ISR/_FIQ_ISR:<br /> ; Save the critical context<br /> STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register<br /> MRS R11, SPSR ; Save the SPSR into R11<br /> ; Get the number of the highest priority active IRQ/FIQ<br /> LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR<br /> LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register<br /> AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number<br /> ; Jump to relevant subroutine handler<br /> LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8<br /> NOP ; To index the table by the PC<br /> ; Table of handler start addresses<br /> .word IRQ0handler ;For IRQ0 of BANK0<br /> .word IRQ1handler<br /> .word IRQ2handler<br /> &lt;/nowiki&gt;</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-25T16:28:48Z

<p>Richarsm: /* Example Assembly */</p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> Data Sheet is located at http://www.ti.com/lit/pdf/spruh73<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.<br /> <br /> Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide<br /> <br /> === Instruction Set ===<br /> Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)<br /> <br /> ==== Four instruction classes ====<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> ==== Instruction Syntax ====<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r3, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3<br /> <br /> ==== Example Assembly ====<br /> &lt;code&gt;<br /> ;INTC_SIR_IRQ/INTC_SIR_FIQ register address<br /> INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044<br /> ; ACTIVEIRQ bit field mask to get only the bit field<br /> ACTIVEIRQ_MASK .equ 0x7F<br /> _IRQ_ISR/_FIQ_ISR:<br /> ; Save the critical context<br /> STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register<br /> MRS R11, SPSR ; Save the SPSR into R11<br /> ; Get the number of the highest priority active IRQ/FIQ<br /> LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR<br /> LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register<br /> AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number<br /> ; Jump to relevant subroutine handler<br /> LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8<br /> NOP ; To index the table by the PC<br /> ; Table of handler start addresses<br /> .word IRQ0handler ;For IRQ0 of BANK0<br /> .word IRQ1handler<br /> .word IRQ2handler<br /> &lt;/code&gt;</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-25T16:28:24Z

<p>Richarsm: Added example assembly</p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> Data Sheet is located at http://www.ti.com/lit/pdf/spruh73<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.<br /> <br /> Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide<br /> <br /> === Instruction Set ===<br /> Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)<br /> <br /> ==== Four instruction classes ====<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> ==== Instruction Syntax ====<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r3, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3<br /> <br /> ==== Example Assembly ====<br /> ;INTC_SIR_IRQ/INTC_SIR_FIQ register address<br /> INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044<br /> ; ACTIVEIRQ bit field mask to get only the bit field<br /> ACTIVEIRQ_MASK .equ 0x7F<br /> _IRQ_ISR/_FIQ_ISR:<br /> ; Save the critical context<br /> STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register<br /> MRS R11, SPSR ; Save the SPSR into R11<br /> ; Get the number of the highest priority active IRQ/FIQ<br /> LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR<br /> LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register<br /> AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number<br /> ; Jump to relevant subroutine handler<br /> LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8<br /> NOP ; To index the table by the PC<br /> ; Table of handler start addresses<br /> .word IRQ0handler ;For IRQ0 of BANK0<br /> .word IRQ1handler<br /> .word IRQ2handler</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-25T16:24:31Z

<p>Richarsm: Added link to assembly guide</p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> Data Sheet is located at http://www.ti.com/lit/pdf/spruh73<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.<br /> <br /> Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide<br /> <br /> === Instruction Set ===<br /> Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)<br /> <br /> ==== Four instruction classes ====<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> ==== Instruction Syntax ====<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r3, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-25T16:15:58Z

<p>Richarsm: Added data sheet link.</p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> Data Sheet is located at http://www.ti.com/lit/pdf/spruh73<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.<br /> <br /> === Instruction Set ===<br /> Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)<br /> <br /> ==== Four instruction classes ====<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> ==== Instruction Syntax ====<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r3, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-18T13:18:45Z

<p>Richarsm: </p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.<br /> <br /> === Instruction Set ===<br /> Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)<br /> <br /> ==== Four instruction classes ====<br /> * Arithmetic<br /> * Logical<br /> * Flow Control<br /> * Register Load/Store<br /> <br /> ==== Instruction Syntax ====<br /> * Mnemonic, followed by comma separated parameter list<br /> * Parameters can be a register, label, immediate value, or constant table entry<br /> * Example<br /> ** SUB r3, r3, 10 <br /> ** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-18T12:04:37Z

<p>Richarsm: </p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone Programmable Real-time Unit ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-18T12:03:53Z

<p>Richarsm: </p> <hr /> <div>The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> == BeagleBone PRU ==<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-18T12:01:41Z

<p>Richarsm: </p> <hr /> <div>== BeagleBone PRU ==<br /> The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> [[File:PRUSS.png|AM335x PRUSS]]<br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-18T12:00:43Z

<p>Richarsm: </p> <hr /> <div>== BeagleBone PRU ==<br /> The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> &lt;gallery&gt;<br /> File:PRUSS.png|AM335x PRUSS<br /> &lt;/gallery&gt;<br /> <br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.</div>

Richarsm http://elinux.org/File:PRUSS.png 2013-04-18T12:00:20Z

<p>Richarsm: AM335x PRU Diagram</p> <hr /> <div>AM335x PRU Diagram</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-18T11:58:23Z

<p>Richarsm: </p> <hr /> <div>== BeagleBone PRU ==<br /> The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> <br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> <br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> &lt;gallery&gt;<br /> File:http://i.imgur.com/vgOiatO.png|AM335x PRUSS<br /> &lt;/gallery&gt;<br /> <br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set<br /> <br /> There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.<br /> <br /> === Software examples ===<br /> BeagleBoard/TI has provided example C programs that utilize the PRU on [https://github.com/beagleboard/am335x_pru_package github.]<br /> <br /> These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.</div>

Richarsm http://elinux.org/BeagleBone_PRU_Notes 2013-04-18T11:48:22Z

<p>Richarsm: Created page with &quot;== BeagleBone PRU == The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU). This i...&quot;</p> <hr /> <div>== BeagleBone PRU ==<br /> The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).<br /> This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.<br /> Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.<br /> <br /> === PRU capabilities ===<br /> &lt;gallery&gt;<br /> File:http://i.imgur.com/vgOiatO.png|AM335x PRUSS<br /> &lt;/gallery&gt;<br /> <br /> <br /> * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).<br /> * 8KB data memory and 8KB instruction memory<br /> * 12KB shared RAM<br /> * A small, deterministic instruction set</div>

Richarsm http://elinux.org/ECE497_SPI_Project 2012-11-08T20:39:25Z

<p>Richarsm: /* Installation Instructions */</p> <hr /> <div>[[Category:ECE497 |Project]]<br /> Team members: [[user:Richarsm|Sean Richardson]], [[user:larmorgs|Greg Larmore]]<br /> <br /> == Grading Template ==<br /> I'm using the following template to grade. Each slot is 10 points.<br /> 0 = Missing, 5=OK, 10=Wow!<br /> <br /> &lt;pre style=&quot;color:red&quot;&gt;<br /> 05 Executive Summary (Good start)<br /> 02 Installation Instructions <br /> 00 User Instructions (Missing)<br /> 00 Highlights (Missing)<br /> 00 Theory of Operation (Missing)<br /> 00 Work Breakdown<br /> 00 Future Work<br /> 00 Conclusions<br /> 00 Demo<br /> 00 Late<br /> Comments: I'm looking forward to seeing this.<br /> <br /> Score: 07/100<br /> &lt;/pre&gt;<br /> <br /> == Executive Summary ==<br /> <br /> For this project we want to further improve documentation available for SPI with the Beagle Bone. In the process of our information gathering we will connect two different products that use SPI, one being an SPI radio interface and the other being a SPI LED strand.<br /> <br /> So far there exists documentation for the [http://elinux.org/BeagleBoard/SPI BeagleBoard/SPI]. There also exists other documentation regarding the SPI specifications.<br /> <br /> The documentation is lacking for the current Beagle Bone platform interfacing with SPI. Additionally there exists virtually no documentation for using a Beagle device with the LPD8806 LED controller.<br /> <br /> In conclusion this project should help the Beagle community in general with information sharing and usable research.<br /> <br /> == Installation Instructions ==<br /> <br /> The kernel driver for SPI is installed in the A6A version of the beagle bone.<br /> <br /> We have integrated some code to work with a SPI radio device &lt;span style=&quot;color:red&quot;&gt;(What radio device?)&lt;/span&gt;. The code is located at [https://github.com/larmorgs/ece497/tree/master/Project github].<br /> <br /> To get started hook up pins 30 (D12) and 31 (A13) to SPI Data (sometimes referred to as Master) and SPI clock. <br /> <br /> [[File:Bone_P9_pinout.jpg]]<br /> <br /> Then echo 0 into both:<br /> beagle$ '''echo 0 &gt; /sys/kernel/debug/omap_mux/spi0_d1'''<br /> beagle$ '''echo 0 &gt; /sys/kernel/debug/omap_mux/spi0_sclk''' <br /> <br /> to select the pin mux for SPI.<br /> <br /> == Work Breakdown ==<br /> <br /> So far we have done research on how Linux interfaces with SPI and we have integrated the SPI interface with current code that we have for an SPI radio. We also have explored methods of interfacing the SPI LED strip with a user to create a pleasant experience, such as creating a website to change the colors, or adding a possible twitter reader that would change the lights based on tweets.<br /> <br /> == Future Work ==<br /> <br /> We want to develop a driver that will interface with SPI and potentially create a sysfs userspace utility for the LED strip.<br /> <br /> == Conclusions ==<br /> <br /> The SPI interface is not well developed in Linux and can use some work progressing it. We have taken on the task of getting these two devices to work in an easier manner.</div>

Richarsm http://elinux.org/ECE497_SPI_Project 2012-11-08T20:08:27Z

<p>Richarsm: /* Installation Instructions */</p> <hr /> <div>[[Category:ECE497 |Project]]<br /> Team members: [[user:Richarsm|Sean Richardson]], [[user:larmorgs|Greg Larmore]]<br /> <br /> == Grading Template ==<br /> I'm using the following template to grade. Each slot is 10 points.<br /> 0 = Missing, 5=OK, 10=Wow!<br /> <br /> &lt;pre style=&quot;color:red&quot;&gt;<br /> 05 Executive Summary (Good start)<br /> 02 Installation Instructions <br /> 00 User Instructions (Missing)<br /> 00 Highlights (Missing)<br /> 00 Theory of Operation (Missing)<br /> 00 Work Breakdown<br /> 00 Future Work<br /> 00 Conclusions<br /> 00 Demo<br /> 00 Late<br /> Comments: I'm looking forward to seeing this.<br /> <br /> Score: 07/100<br /> &lt;/pre&gt;<br /> <br /> == Executive Summary ==<br /> <br /> For this project we want to further improve documentation available for SPI with the Beagle Bone. In the process of our information gathering we will connect two different products that use SPI, one being an SPI radio interface and the other being a SPI LED strand.<br /> <br /> So far there exists documentation for the [http://elinux.org/BeagleBoard/SPI BeagleBoard/SPI]. There also exists other documentation regarding the SPI specifications.<br /> <br /> The documentation is lacking for the current Beagle Bone platform interfacing with SPI. Additionally there exists virtually no documentation for using a Beagle device with the LPD8806 LED controller.<br /> <br /> In conclusion this project should help the Beagle community in general with information sharing and usable research.<br /> <br /> == Installation Instructions ==<br /> <br /> The kernel driver for SPI is installed in the A6A version of the beagle bone.<br /> <br /> We have integrated some code to work with a SPI radio device &lt;span style=&quot;color:red&quot;&gt;(What radio device?)&lt;/span&gt;. The code is located at [https://github.com/larmorgs/ece497/tree/master/Project github].<br /> <br /> To get started hook up pins 30 (D12) and 31 (A13) to SPI Data (sometimes referred to as Master) and SPI clock. <br /> <br /> [[File:Bone_P9_pinout.jpg]]<br /> <br /> Then echo 0 into both:<br /> beagle$ '''echo 0 &gt; /sys/kernel/debug/omap_mux/spi1_d1'''<br /> beagle$ '''echo 0 &gt; /sys/kernel/debug/omap_mux/spi1_sclk''' <br /> <br /> to select the pin mux for SPI.<br /> <br /> == Work Breakdown ==<br /> <br /> So far we have done research on how Linux interfaces with SPI and we have integrated the SPI interface with current code that we have for an SPI radio. We also have explored methods of interfacing the SPI LED strip with a user to create a pleasant experience, such as creating a website to change the colors, or adding a possible twitter reader that would change the lights based on tweets.<br /> <br /> == Future Work ==<br /> <br /> We want to develop a driver that will interface with SPI and potentially create a sysfs userspace utility for the LED strip.<br /> <br /> == Conclusions ==<br /> <br /> The SPI interface is not well developed in Linux and can use some work progressing it. We have taken on the task of getting these two devices to work in an easier manner.</div>

Richarsm http://elinux.org/EBC_Exercise_25_Configuring_U-boot 2012-11-08T16:12:10Z

<p>Richarsm: /* Assignment */ spelling</p> <hr /> <div>[[Category:ECE497]]<br /> [[Category:BeagleBoard]]<br /> {{YoderHead}}<br /> <br /> This follows the approach taken in [[EBC Exercise 13 Configuring the Kernel]]. We'll use '''bitbake''' to get the source files for U-boot and then we'll edit them.<br /> <br /> == bitbake ==<br /> <br /> When you did [[EBC Exercise 22 Cross-Compiling and Finding the Right Kernel]] u-boot was downloaded and compiled. If you used the default configure, the source code was removed once it was done. Check and see:<br /> <br /> host$ '''cd ~/BeagleBoard/oe/build/tmp-angstrom_v2012_05-eglibc/work/beagleboard-angstrom-linux-gnueabi/'''<br /> host$ '''ls'''<br /> <br /> You should see a directory starting with &lt;code&gt;u-boot-&lt;/code&gt;. The rest of the name tells what version you have. Change to that directory and see what's there:<br /> <br /> host$ '''cd u-boot-*'''<br /> host$ '''ls'''<br /> <br /> If you see a '''git''' directory, you are in luck. If you see just a '''temp''' directory you need to go back to [[EBC Exercise 22 Cross-Compiling and Finding the Right Kernel]] and get it installed.<br /> <br /> Once you have the '''git''' directory, ''cd'' to it and look around.<br /> <br /> == Compiling U-boot ==<br /> <br /> You can now compile U-boot. <br /> <br /> host$ '''source ~/.oe/crossCompileEnv.sh'''<br /> host$ '''make'''<br /> host$ '''scp u-boot.bin root@beagle:.'''<br /> <br /> On the beagle, first be sure the FAT partition is mounted<br /> beagle$ '''cd /media/'''<br /> beagle$ '''mkdir mmcblk0p1'''<br /> beagle$ '''mount /dev/mmcblk0p1 mmcblk0p1/'''<br /> beagle$ '''cd mmcblk0p1/'''<br /> beagle$ '''ls -ls'''<br /> total 354<br /> 2 drwxr-xr-x 4 root root 2048 May 16 15:29 Docs<br /> 2 drwxr-xr-x 5 root root 2048 May 16 15:29 Drivers<br /> 6 -rwxr-xr-x 1 root root 5829 Aug 14 10:10 LICENSE.txt<br /> 84 -rwxr-xr-x 1 root root 85058 Aug 14 08:19 MLO<br /> 14 -rwxr-xr-x 1 root root 13976 Aug 14 10:10 README.htm<br /> 2 -rwxr-xr-x 1 root root 27 Aug 14 10:23 Uenv.txt<br /> 2 -rwxr-xr-x 1 root root 178 Aug 14 10:10 autorun.inf<br /> 2 -rwxr-xr-x 1 root root 171 Aug 14 10:10 info.txt<br /> 238 -rwxr-xr-x 1 root root 241948 Aug 14 08:19 u-boot.img<br /> 2 -rwxr-xr-x 1 root root 33 Aug 14 10:23 uEnv.txt.orig<br /> <br /> Make a backup of the original u-boot.<br /> beagle$ '''cp u-boot.bin u-boot.bin.orig'''<br /> beagle$ '''cp ~/u-boot.bin .'''<br /> beagle$ shutdown -r now<br /> <br /> You should now be running the new u-boot.<br /> <br /> == &lt;span style=&quot;color:green&quot;&gt;Assignment&lt;/span&gt; ==<br /> <br /> <br /> # Modify u-boot to include your initials in the prompt. (Hint: Look for the '''omap3_beagle.h''' file for the xM or '''am335x_evm.h''' for the bone.)<br /> # Learn what is done when the '''boot''' command is entered in u-boot.<br /> # Find where the code for boot is defined in the u-boot source.<br /> <br /> Hint:<br /> u-boot# '''help boot'''<br /> boot - boot default, i.e., run 'bootcmd'<br /> <br /> Usage:<br /> boot <br /> u-boot# '''print bootcmd'''<br /> bootcmd=if mmc rescan ${mmcdev}; then if userbutton; then setenv bootenv user.txt;fi;echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loaduimage; then run mmcboot;fi;fi;run nandboot;<br /> <br /> {{YoderFoot}}</div>

Richarsm http://elinux.org/ECE497_Contributions_and_Project_Status 2012-11-06T16:51:06Z

<p>Richarsm: /* Project Status */ added contributions for Sean</p> <hr /> <div>[[Category:ECE497 |Contributions]]<br /> {{YoderHead}}<br /> <br /> == Fall 2012 ==<br /> <br /> === Project Status ===<br /> <br /> Please edit this page and add your project to this list. Copy my [[ECE497 Project Template]] to your own eLinux page and include the title of your project in the name of the page. <br /> <br /> Please make the list alphabetical by family name.<br /> <br /> Take a look at what you and others have contributed.<br /> <br /> {|<br /> |- <br /> ! Name<br /> ! Contributions<br /> ! Project<br /> ! git repository<br /> |-<br /> | [[User:atniptw | Tom Atnip]]<br /> | <br /> | [[ECE497 Beagle VNS | Beagle VNS]]<br /> | [https://github.com/atniptw/ atniptw]<br /> |-<br /> | [[User:larmorgs | Greg Larmore]]<br /> | <br /> | [[ECE497 SPI Project | SPI Project]]<br /> | [https://github.com/larmorgs/ larmorgs]<br /> |-<br /> | [[User:jessebrannon | Jesse Brannon]]<br /> | <br /> | [[ECE497 Project Rover | Rover]]<br /> | [https://github.com/brannojs/ brannojs]<br /> |-<br /> | [[User:Xinyu1991 | Xinyu Cheng]]<br /> | [[Special:Contributions/Xinyu1991|contrib]]<br /> | [[ECE497_Project:_Kinect | Kinect]]<br /> | [https://github.com/xinyu1991/ Xinyu Cheng]<br /> |-<br /> | [[User:correlbn | Bryan Correll]]<br /> | [[Special:Contributions/correlbn|contrib]]<br /> | [[BeagleBone PRU | BeagleBone PRU]]<br /> | [https://github.com/correlbn/My-Beagle-Project/ Correlbn]<br /> |-<br /> | [[User:draneaw | Alex Drane]]<br /> | <br /> | [[ECE497 draneaw Project | My Beagle Project]]<br /> | [https://github.com/draneaw/My-Beagle-Project draneaw]<br /> |-<br /> | [[User:duganje | Josh Dugan]]<br /> | [[Special:Contributions/duganje|contrib]]<br /> | [[ECE497 Project: XBee|XBee]]<br /> | [https://github.com/duganje/ duganje]<br /> |-<br /> | [[User:Geislekj | Kevin Geisler]]<br /> | <br /> | [[ECE497 Beagle VNS | Beagle VNS]]<br /> | [https://github.com/geislekj/ geislekj]<br /> | <br /> |-<br /> | [[User:chris.good | Christopher A Good]]<br /> | [[Special:Contributions/Chris.good|contrib]]<br /> | [[ECE497 Project RoverGUI | RoverGUI]]<br /> | [https://github.com/goodca/ goodca]<br /> | <br /> |-<br /> | [[User:hansenrl | Ross Hansen]]<br /> | [[Special:Contributions/hansenrl|contrib]]<br /> | [[ECE497 Project Rover | Rover]]<br /> | [https://github.com/hansenrl/ Hansenrl]<br /> | <br /> |-<br /> | [[User:jungeml | Michael Junge]]<br /> | [[Special:Contributions/jungeml|contrib]]<br /> | [[ECE497 Project Rover | Rover]]<br /> | [https://github.com/jungeml/ Jungeml]<br /> |-<br /> |<br /> |-<br /> | [[User:Lix | Xia Li]]<br /> | [[Special:Contributions/Lix|contrib]]<br /> | [[ECE497 Lix Project | My Beagle Project]]<br /> | [https://github.com/1984xiali/ xiali]<br /> |-<br /> | [[User:mmoravec | Matthew Moravec]]<br /> | [[Special:Contributions/mmoravec|contrib]]<br /> | [[ECE497 Project: XBee|XBee]]<br /> | [https://github.com/mmoravec/ mmoravec]<br /> |-<br /> | [[User:ngop | Peter Ngo]]<br /> | <br /> | [[ECE497 ngop Project: Beaglebone PRU|Beaglebone PRU]]<br /> | [https://github.com/ngop/ ngop]<br /> |<br /> |-<br /> | [[User:shinnsm|Stephen Shinn]]<br /> | [[Special:Contributions/shinnsm|contrib]]<br /> | [[ECE497 Project: XBee|XBee]]<br /> | [https://github.com/shinnsm shinnsm]<br /> |-<br /> | [[User:Yoder | Mark A. Yoder]]<br /> | [[Special:Contributions/Yoder | contrib]]<br /> | [[ECE497 Project Template | My Beagle Project]]<br /> | [https://github.com/MarkAYoder MarkAYoder]<br /> |-<br /> | [[User:Popenhjc | James Popenhagen]]<br /> | <br /> | [[BeagleBone PRU | BeagleBone PRU]]<br /> | [https://github.com/popenhjc/ popenhjc]<br /> |-<br /> | [[User:Whiteer | Elias White]]<br /> | <br /> | [[ECE497 SLAM via ROS | My Beagle Project]]<br /> | [https://github.com/whiteer whiteer]<br /> |-<br /> | [[User:ruff | Ruffin White]]<br /> | <br /> | [[ECE497 Beagle VNS | Beagle VNS]]<br /> | [https://github.com/ruffsl/ ruffsl]<br /> |<br /> |-<br /> | [[User:Richarsm | Sean Richardson]]<br /> | [[Special:Contributions/Richarsm|contrib]]<br /> | [[ECE497 SPI Project | SPI Project]]<br /> | [https://github.com/seanrich Sean Richardson]<br /> |-<br /> | [[User:Millerap | Andrew Miller]]<br /> |<br /> | [[ECE 497 millerap Project | My Beagle Project]]<br /> | [https://github.com/millerap millerap]<br /> |-| <br /> | [[User:Astroricks | Yue Zhang]]<br /> | <br /> | [[ECE497 Yue Zhang Project | My Beagle Project]]<br /> | [https://github.com/Astroricks/Beagle-Project Yue Zhang]<br /> |-<br /> | [[User:Lobdeljt | John Lobdell]]<br /> | <br /> | [[ECE 497 lobdeljt Project | My Beagle Project]]<br /> | [https://github.com/jtlobdell jtlobdell]<br /> |-<br /> |<br /> |}<br /> <br /> == Winter 2011-2012 ==<br /> <br /> === Contributions ===<br /> <br /> # [[Special:Contributions/Yuming | Yuming Cao]]<br /> # [[Special:Contributions/Yifei | Yifei Li]]<br /> # [[Special:Contributions/Harrisgw | Greg Harrison]]<br /> # [[Special:Contributions/mac | Jack Ma]]<br /> # [[Special:Contributions/Gemini91 | Guanqun Wang]]<br /> # [[Special:Contributions/Yanj | Mona Yan]]<br /> # [[Special:Contributions/Yoder | Mark A. Yoder]]<br /> # [[Special:Contributions/Yuhasmj | Michael Yuhas]]<br /> # [[Special:Contributions/Ziyi Zhang | Ziyi Zhang]]<br /> # [[Special:Contributions/Zitnikdj | David Zitnik]]<br /> # [[Special:Contributions/Zitnikdj | Alex Drane]]<br /> # [[Special:Contributions/jessebrannon | Jesse Brannon]]<br /> # [[Special:Contributions/larmorgs | Greg Larmore]]<br /> # [[Special:Contributions/jungeml | Michael Junge]]<br /> # [[Special:Contributions/millerap | Andrew Miller]]<br /> # [[Special:Contributions/correlbn | Bryan Correll]]<br /> <br /> === Project Status ===<br /> <br /> # [[User:Yoder | Mark A. Yoder]], [[ECE497 Project Template | My Beagle Project]]<br /> # [[user:Yanj|Mona Yan]] and [[user:Harrisgw| Greg Harrison]], [[PS EYE QT PROJECT | Playstation Eye Audio with Qt]]<br /> # [[user:Caogecym | Yuming Cao]] and [[user:Ziyi Zhang | Ziyi Zhang]], [[Node.js Weather Station]]<br /> # [[user:Yifei| Yifei Li]] and [[user:Gemini91| Guanqun Wang]], [[ Kinect Project | Play games using Kinect on Beagleboard]]<br /> # [[user:Yuhasmj| Michael J. Yuhas]] and [[user:mac | Jack Ma]], [[ Multiple Partitions via U-boot | Multiple Partitions via U-boot ]]<br /> # [[user:Zitnikdj| David Zitnik]], [[ ECE497 Project: Twitter Java Application | Twitter Java Application ]]<br /> <br /> <br /> {{YoderFoot}}</div>

Richarsm http://elinux.org/ECE497_Contributions_and_Project_Status 2012-11-06T16:49:46Z

<p>Richarsm: /* Project Status */ updated project for Sean and Greg</p> <hr /> <div>[[Category:ECE497 |Contributions]]<br /> {{YoderHead}}<br /> <br /> == Fall 2012 ==<br /> <br /> === Project Status ===<br /> <br /> Please edit this page and add your project to this list. Copy my [[ECE497 Project Template]] to your own eLinux page and include the title of your project in the name of the page. <br /> <br /> Please make the list alphabetical by family name.<br /> <br /> Take a look at what you and others have contributed.<br /> <br /> {|<br /> |- <br /> ! Name<br /> ! Contributions<br /> ! Project<br /> ! git repository<br /> |-<br /> | [[User:atniptw | Tom Atnip]]<br /> | <br /> | [[ECE497 Beagle VNS | Beagle VNS]]<br /> | [https://github.com/atniptw/ atniptw]<br /> |-<br /> | [[User:larmorgs | Greg Larmore]]<br /> | <br /> | [[ECE497 SPI Project | SPI Project]]<br /> | [https://github.com/larmorgs/ larmorgs]<br /> |-<br /> | [[User:jessebrannon | Jesse Brannon]]<br /> | <br /> | [[ECE497 Project Rover | Rover]]<br /> | [https://github.com/brannojs/ brannojs]<br /> |-<br /> | [[User:Xinyu1991 | Xinyu Cheng]]<br /> | [[Special:Contributions/Xinyu1991|contrib]]<br /> | [[ECE497_Project:_Kinect | Kinect]]<br /> | [https://github.com/xinyu1991/ Xinyu Cheng]<br /> |-<br /> | [[User:correlbn | Bryan Correll]]<br /> | [[Special:Contributions/correlbn|contrib]]<br /> | [[BeagleBone PRU | BeagleBone PRU]]<br /> | [https://github.com/correlbn/My-Beagle-Project/ Correlbn]<br /> |-<br /> | [[User:draneaw | Alex Drane]]<br /> | <br /> | [[ECE497 draneaw Project | My Beagle Project]]<br /> | [https://github.com/draneaw/My-Beagle-Project draneaw]<br /> |-<br /> | [[User:duganje | Josh Dugan]]<br /> | [[Special:Contributions/duganje|contrib]]<br /> | [[ECE497 Project: XBee|XBee]]<br /> | [https://github.com/duganje/ duganje]<br /> |-<br /> | [[User:Geislekj | Kevin Geisler]]<br /> | <br /> | [[ECE497 Beagle VNS | Beagle VNS]]<br /> | [https://github.com/geislekj/ geislekj]<br /> | <br /> |-<br /> | [[User:chris.good | Christopher A Good]]<br /> | [[Special:Contributions/Chris.good|contrib]]<br /> | [[ECE497 Project RoverGUI | RoverGUI]]<br /> | [https://github.com/goodca/ goodca]<br /> | <br /> |-<br /> | [[User:hansenrl | Ross Hansen]]<br /> | [[Special:Contributions/hansenrl|contrib]]<br /> | [[ECE497 Project Rover | Rover]]<br /> | [https://github.com/hansenrl/ Hansenrl]<br /> | <br /> |-<br /> | [[User:jungeml | Michael Junge]]<br /> | [[Special:Contributions/jungeml|contrib]]<br /> | [[ECE497 Project Rover | Rover]]<br /> | [https://github.com/jungeml/ Jungeml]<br /> |-<br /> |<br /> |-<br /> | [[User:Lix | Xia Li]]<br /> | [[Special:Contributions/Lix|contrib]]<br /> | [[ECE497 Lix Project | My Beagle Project]]<br /> | [https://github.com/1984xiali/ xiali]<br /> |-<br /> | [[User:mmoravec | Matthew Moravec]]<br /> | [[Special:Contributions/mmoravec|contrib]]<br /> | [[ECE497 Project: XBee|XBee]]<br /> | [https://github.com/mmoravec/ mmoravec]<br /> |-<br /> | [[User:ngop | Peter Ngo]]<br /> | <br /> | [[ECE497 ngop Project: Beaglebone PRU|Beaglebone PRU]]<br /> | [https://github.com/ngop/ ngop]<br /> |<br /> |-<br /> | [[User:shinnsm|Stephen Shinn]]<br /> | [[Special:Contributions/shinnsm|contrib]]<br /> | [[ECE497 Project: XBee|XBee]]<br /> | [https://github.com/shinnsm shinnsm]<br /> |-<br /> | [[User:Yoder | Mark A. Yoder]]<br /> | [[Special:Contributions/Yoder | contrib]]<br /> | [[ECE497 Project Template | My Beagle Project]]<br /> | [https://github.com/MarkAYoder MarkAYoder]<br /> |-<br /> | [[User:Popenhjc | James Popenhagen]]<br /> | <br /> | [[BeagleBone PRU | BeagleBone PRU]]<br /> | [https://github.com/popenhjc/ popenhjc]<br /> |-<br /> | [[User:Whiteer | Elias White]]<br /> | <br /> | [[ECE497 SLAM via ROS | My Beagle Project]]<br /> | [https://github.com/whiteer whiteer]<br /> |-<br /> | [[User:ruff | Ruffin White]]<br /> | <br /> | [[ECE497 Beagle VNS | Beagle VNS]]<br /> | [https://github.com/ruffsl/ ruffsl]<br /> |<br /> |-<br /> | [[User:Richarsm | Sean Richardson]]<br /> | <br /> | [[ECE497 SPI Project | SPI Project]]<br /> | [https://github.com/seanrich Sean Richardson]<br /> |-<br /> | [[User:Millerap | Andrew Miller]]<br /> |<br /> | [[ECE 497 millerap Project | My Beagle Project]]<br /> | [https://github.com/millerap millerap]<br /> |-| <br /> | [[User:Astroricks | Yue Zhang]]<br /> | <br /> | [[ECE497 Yue Zhang Project | My Beagle Project]]<br /> | [https://github.com/Astroricks/Beagle-Project Yue Zhang]<br /> |-<br /> | [[User:Lobdeljt | John Lobdell]]<br /> | <br /> | [[ECE 497 lobdeljt Project | My Beagle Project]]<br /> | [https://github.com/jtlobdell jtlobdell]<br /> |-<br /> |<br /> |}<br /> <br /> == Winter 2011-2012 ==<br /> <br /> === Contributions ===<br /> <br /> # [[Special:Contributions/Yuming | Yuming Cao]]<br /> # [[Special:Contributions/Yifei | Yifei Li]]<br /> # [[Special:Contributions/Harrisgw | Greg Harrison]]<br /> # [[Special:Contributions/mac | Jack Ma]]<br /> # [[Special:Contributions/Gemini91 | Guanqun Wang]]<br /> # [[Special:Contributions/Yanj | Mona Yan]]<br /> # [[Special:Contributions/Yoder | Mark A. Yoder]]<br /> # [[Special:Contributions/Yuhasmj | Michael Yuhas]]<br /> # [[Special:Contributions/Ziyi Zhang | Ziyi Zhang]]<br /> # [[Special:Contributions/Zitnikdj | David Zitnik]]<br /> # [[Special:Contributions/Zitnikdj | Alex Drane]]<br /> # [[Special:Contributions/jessebrannon | Jesse Brannon]]<br /> # [[Special:Contributions/larmorgs | Greg Larmore]]<br /> # [[Special:Contributions/jungeml | Michael Junge]]<br /> # [[Special:Contributions/millerap | Andrew Miller]]<br /> # [[Special:Contributions/correlbn | Bryan Correll]]<br /> <br /> === Project Status ===<br /> <br /> # [[User:Yoder | Mark A. Yoder]], [[ECE497 Project Template | My Beagle Project]]<br /> # [[user:Yanj|Mona Yan]] and [[user:Harrisgw| Greg Harrison]], [[PS EYE QT PROJECT | Playstation Eye Audio with Qt]]<br /> # [[user:Caogecym | Yuming Cao]] and [[user:Ziyi Zhang | Ziyi Zhang]], [[Node.js Weather Station]]<br /> # [[user:Yifei| Yifei Li]] and [[user:Gemini91| Guanqun Wang]], [[ Kinect Project | Play games using Kinect on Beagleboard]]<br /> # [[user:Yuhasmj| Michael J. Yuhas]] and [[user:mac | Jack Ma]], [[ Multiple Partitions via U-boot | Multiple Partitions via U-boot ]]<br /> # [[user:Zitnikdj| David Zitnik]], [[ ECE497 Project: Twitter Java Application | Twitter Java Application ]]<br /> <br /> <br /> {{YoderFoot}}</div>

Richarsm http://elinux.org/User:Richarsm 2012-11-06T13:49:20Z

<p>Richarsm: </p> <hr /> <div>Student in Embedded Linux ECE467.<br /> <br /> I also did [http://elinux.org/Adafruit:_LED_Strip_LPD8806 LED Strip LPD8806]<br /> <br /> [[Category:ECE497 |Ur]]</div>

Richarsm http://elinux.org/User:Richarsm 2012-11-06T13:49:09Z

<p>Richarsm: </p> <hr /> <div>Student in Embedded Linux ECE467.<br /> <br /> I also did [http://elinux.org/Adafruit:_LED_Strip_LPD8806 | LED Strip LPD8806]<br /> <br /> [[Category:ECE497 |Ur]]</div>

Richarsm http://elinux.org/User:Richarsm 2012-11-06T13:48:54Z

<p>Richarsm: </p> <hr /> <div>Student in Embedded Linux ECE467.<br /> I also did [[http://elinux.org/Adafruit:_LED_Strip_LPD8806 | LED Strip LPD8806]]<br /> <br /> [[Category:ECE497 |Ur]]</div>

Richarsm http://elinux.org/User:Richarsm 2012-11-06T13:48:27Z

<p>Richarsm: </p> <hr /> <div>Student in Embedded Linux ECE467.<br /> I also did [[http://elinux.org/Adafruit:_LED_Strip_LPD8806]]<br /> <br /> [[Category:ECE497 |Ur]]</div>

Richarsm http://elinux.org/User:Richarsm 2012-11-06T13:46:43Z

<p>Richarsm: updated category</p> <hr /> <div>Student in Embedded Linux ECE497.<br /> <br /> [[Category:ECE497 | Ur]]</div>

Richarsm http://elinux.org/EBC_Exercise_08_Installing_Development_Tools 2012-11-05T05:36:53Z

<p>Richarsm: /* reboot */ we should use /dev/ttyUSB1 instead of USB0</p> <hr /> <div>[[Category:ECE497]]<br /> {{YoderHead}}<br /> <br /> Early in the class most of the exercises we will do will all run on the BeagleBoard. You'll be able to edit ([http://projects.gnome.org/gedit/ gedit]), compile ([http://gcc.gnu.org/ gcc]) and run all on the Beagle. Later, when we start compiling the kernel [http://www.kernel.org/] or the boot loader, ([http://www.denx.de/wiki/U-Boot U-boot]) you will need to cross compile on a Linux machine and copy the results to the Beagle.<br /> <br /> The purpose of this exercise is to install all the tools needed for compiling on your host so they will be ready when you need them.<br /> <br /> Instructions for building Ångström are given [http://www.angstrom-distribution.org/building-angstrom here]; however there are a few changes you have to make. Here's what I did.<br /> <br /> '''Tip:''' Run this exercise using a wired connection if you can. The Ubuntu wireless driver can be finicky, and if it stops working you'll have to restart some of this.<br /> <br /> == The Kernel ==<br /> <br /> These instructions have been tested for the 3.2.25 kernel.<br /> <br /> === download ===<br /> These are notes are based on [https://github.com/beagleboard/kernel/blob/6682025752d0b807119c1e363a0b1b9bfe2ab453/README.md Beagleboard kernel git site].<br /> <br /> First download the tools needed to compile the kernel. This took about 25 seconds.<br /> host$ '''sudo apt-get install -y git lzop gcc-arm-linux-gnueabi uboot-mkimage'''<br /> <br /> Next download the tools to get the kernel and the patches needed to make it run on the beagle. (2.5 seconds)<br /> host$ '''cd ~/BeagleBoard'''<br /> host$ '''git clone git://github.com/beagleboard/kernel.git'''<br /> host$ '''git checkout 6a7c4284a16fed3dae87f4aef78b59c902e4da84 -b beaglebone-3.2'''<br /> <br /> Next download the kernel and the patches. Before running '''./patch/sh''', take a look at it. Can you figure out what it's doing? Also look at '''patch_script.sh''', it's where the details are. The downloading/patching process takes some 39 minutes.<br /> host$ '''less patch.sh patch_script.sh'''<br /> host$ '''./patch.sh'''<br /> host$ '''cp patches/beaglebone/defconfig kernel/arch/arm/configs/beaglebone_defconfig<br /> host$ '''wget http://arago-project.org/git/projects/?p=am33x-cm3.git\;a=blob_plain\;f=bin/am335x-pm-firmware.bin\;hb=HEAD -O kernel/firmware/am335x-pm-firmware.bin'''<br /> host$ '''md5sum kernel/firmware/am335x-pm-firmware.bin''' <br /> 17d6a4c24d3cb720aa9ed4522cb891fc kernel/firmware/am335x-pm-firmware.bin<br /> <br /> === compile ===<br /> Once patched you are ready to compile the kernel. The first time takes a while. Mine tool 4 minutes, but I was running on 8 cores. Set the '''-j''X'' ''' to match the number of cores you have. '''uImage''' is the kernel!<br /> host$ '''cd kernel'''<br /> host$ '''make beaglebone_defconfig'''<br /> <br /> Now that you know it's working, let's compile it. First set the paths to find the cross-compiles. Put the following in a file, call it ~/.oe/'''crossCompile.sh'''.<br /> <br /> export ARCH=arm<br /> export CROSS_COMPILE=arm-linux-gnueabi-<br /> Do the above once<br /> <br /> Now ''source'' the file.<br /> host$ '''source ~/.oe/crossCompileEnv.sh'''<br /> Do the above once per terminal session.<br /> <br /> host$ '''make -j9'''<br /> host$ '''make uImage'''<br /> Do the above every time you recompile the kernel<br /> <br /> You also need all the kernel modules. Here we create a directory to install them in. (a few seconds)<br /> host$ '''mkdir ../rootfs'''<br /> host$ '''make INSTALL_MOD_PATH=../rootfs modules_install'''<br /> <br /> === install ===<br /> Copy the kernel and the modules to the Beagle. (a minute or so)<br /> host$ '''cd ..'''<br /> host$ '''scp kernel/arch/arm/boot/uImage root@beagle:/boot/uImage-3.2.25+<br /> host$ '''cd rootfs'''<br /> host$ '''find -H -depth | cpio -o -H crc | ssh root@beagle 'cd /; cpio -id' '''<br /> <br /> Now log into the beagle and move some things around.<br /> host$ '''ssh root@beagle<br /> <br /> This will copy the kernel to the ext4 partition.<br /> beagle$ '''cd /boot'''<br /> beagle$ '''rm uImage'''<br /> beagle$ '''ln -s uImage-3.2.25+ uImage'''<br /> <br /> This will copy to the FAT partition.<br /> beagle$ '''mkdir /media/mmcblk0p1'''<br /> beagle$ '''mount /dev/mmcblk0p1 /media/mmcblk0p1'''<br /> beagle$ '''cp /boot/uImage-3.2.25+ /media/uImage'''<br /> <br /> === reboot ===<br /> Make sure screen is running on your host so you can see the shutdown and boot processes.<br /> host$ '''screen /dev/ttyUSB1 115200'''<br /> <br /> If you get an error try changing making yourself the owner of /dev/ttyUSB1.<br /> host$ '''sudo chown ''yoder:yoder'' /dev/ttyUSB1'''<br /> host$ '''screen /dev/ttyUSB1 115200'''<br /> <br /> Then restart you beagle<br /> beagle$ '''shutdown -r now'''<br /> <br /> If all goes well you will boot into your new kernel.<br /> beagle$ '''uname -a'''<br /> Linux beaglebone 3.2.25+ #1 Fri Oct 19 11:05:28 EDT 2012 armv7l GNU/Linux<br /> <br /> == DAS U-boot ==<br /> These instructions came from [http://www.eewiki.net/display/linuxonarm/Home eewiki].<br /> <br /> === download ===<br /> While we're at it, let's get the boot loader we'll be using. It takes some 3 minutes.<br /> <br /> host$ '''cd ~/BeagleBoard'''<br /> host$ '''git clone git://git.denx.de/u-boot.git'''<br /> host$ '''cd u-boot/'''<br /> host$ '''git checkout v2012.10-rc2 -b tmp'''<br /> <br /> === compile ===<br /> Now configure and build. The first time takes some 4 minutes. After that it's only 5 seconds or so. (Replace '''am335x_evm_config''' with '''omap3_beagle_config''' if you are compiling for the xM.)<br /> host$ '''make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi- am335x_evm_config'''<br /> host$ '''make ARCH=arm CROSS_COMPILE=arm-linux-gnueabi-'''<br /> <br /> === install ===<br /> <br /> host$ '''scp u-boot.img root@beagle:.'''<br /> beagle$ '''mkdir /media/mmcblk0p1'''<br /> beagle$ '''mount /dev/mmcblk0p1 /media/mmcblk0p1'''<br /> beagle$ '''cd /media/mmcblk0p1'''<br /> beagle$ '''mv u-boot.img u-boot.img.orig''' # Save the working u-boot<br /> beagle$ '''cp ~/u-boot.img u-boot.img.new'''<br /> beagle$ '''cp u-boot.img.new u-boot.img'''<br /> Once installed you are ready for u-boot work.<br /> <br /> {{YoderFoot}}</div>

Richarsm http://elinux.org/ECE497_Calendar_and_Exercises 2012-11-05T03:37:41Z

<p>Richarsm: /* Week 7 */ made a link for exercise 25</p> <hr /> <div>[[Category:ECE497 |Calendar]]<br /> [[Category:BeagleBoard]]<br /> {{YoderHead}}<br /> <br /> Here's what you'll need to do for the class. Unless stated otherwise these are individual exercises, not team.<br /> <br /> I'm updating this from last year, so be sure to check the year to be sure it's been refreshed. If the background is white, it hasn't been updated.<br /> <br /> '''All assignments are due the start of the following week. Initially that is a Thursday!'''<br /> <br /> == Week 1 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ffffcc;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Assignment Links<br /> |-<br /> | 1-1<br /> | 30-Aug-2012<br /> | <br /> | Introductions, Demos<br /> | Fire up your Beagle and see it work. Do everything in Exercise 09. Due Friday.<br /> '''[[EBC Exercise 01 Start Here]]''' gives an overview of what we'll be doing over the next few days. Start setting up your Linux development computer now. You can do either a native install, or a virtual machine. [[EBC Exercise 06 Notes on VirtualBox | Here]] and [[EBC Exercise 07 Notes on Installing Ubuntu in VMware Player | here]] are some notes in virtual machine installs. They are out of date. Feel free to update them.<br /> <br /> I suggest Ubuntu 12.04 LTS. Some of the TI software may require it. I may not be able to help with other versions of distributions.<br /> <br /> | [[ECE497 - 32-bit Embedded Linux, Rose-Hulman]]<br /> [[EBC_Exercise_01_Start_Here#The_Linux_host_computer | EBC Exercise 01 Start Here]]<br /> <br /> [[EBC Exercise 02 Out-of-the-Box, Bone]]<br /> <br /> [[EBC Exercise 09 Working With Open Source]]<br /> |-<br /> | 1-2<br /> | 31<br /> | <br /> | General Purpose IO, LEDs and push buttons.<br /> | Set up a Beagle, demo in class. Get reference manuals and clone git repository.<br /> | [[EBC Exercise 03 Installing a Beagle OS]]<br /> <br /> [[EBC Exercise 05 Getting Exercise Support Materials]]<br /> <br /> [[EBC Exercise 10 Flashing an LED]]<br /> |-<br /> | 1-3<br /> | 3-Sept-2012<br /> | <br /> | Interrupts and gpio<br /> | <br /> | [[EBC Exercise 08 Installing Development Tools]]<br /> <br /> [[EBC Exercise 11 gpio Polling and Interrupts]]<br /> |-<br /> | 1-4<br /> | 4<br /> |<br /> | i2c, git<br /> | <br /> | [[EBC Exercise 16 git]]<br /> |-<br /> |<br /> | &quot;<br /> |<br /> |<br /> | Add your project ideas<br /> | [[ECE497 Project Ideas]]<br /> |}<br /> <br /> == Week 2 ==<br /> <br /> {| style=&quot;color:blue; background-color:#eeffff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |- <br /> | 2-1<br /> | 6-Sept<br /> | <br /> | Pulse Width Modulation<br /> | <br /> | [[EBC Exercise 12 I2C]]<br /> <br /> [[EBC Exercise 13 Pulse Width Modulation]]<br /> |-<br /> | 2-2<br /> | 7<br /> | <br /> | Lab Time, Mini Project 01<br /> | Measure gpio and pwm with oscilloscope.<br /> | [[EBC Mini Project 01]]<br /> |-<br /> | 2-3<br /> | 10<br /> |<br /> | gdb, Lab Time<br /> | <br /> | [[EBC Exercise 14 gdb Debugging]]<br /> |-<br /> | 2-4<br /> | 11<br /> | <br /> | Lab Time<br /> | <br /> | <br /> |}<br /> <br /> == Week 3 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ffaaff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 3-1<br /> | 13<br /> | <br /> | make, Mini Project 02<br /> | Flash ETC 2012 image on SD card for xM<br /> | [[EBC Exercise 15 make]]<br /> <br /> [[EBC Mini Project 02]]<br /> <br /> [[EBC Exercise 03 Installing a Beagle OS]]<br /> |-<br /> | 3-2<br /> | 14<br /> | <br /> | Advanced Linux Sound Architecture (ALSA)<br /> | <br /> | [[EBC Exercise 17 Using ALSA for Audio Processing]]<br /> |-<br /> | 3-3<br /> | 17<br /> | <br /> | Using the DSP (c6run)<br /> | <br /> | [[EBC Exercise 18 Using the DSP for Audio Processing]]<br /> |-<br /> | 3-4<br /> | 18<br /> | <br /> | Lab Time, Mini Project 1 demo time<br /> | <br /> | <br /> |}<br /> <br /> == Week 4 ==<br /> <br /> {|style=&quot;color:blue; background-color:#ddffff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 4-1<br /> | 20<br /> | <br /> | Video Processing<br /> | <br /> | [[EBC Exercise 19 DSS2 and sysfs]]<br /> <br /> [[EBC Exercise 20 The Display SubSystem (DSS)]]<br /> |-<br /> | 4-2<br /> | 21<br /> | <br /> | Lab Time<br /> | <br /> | <br /> |-<br /> | 4-3<br /> | 24<br /> | <br /> | Threads<br /> | <br /> | [[EBC Exercise 21 Running Audio and Video]]<br /> |-<br /> | 4-4<br /> | 25<br /> | <br /> | Lab Time<br /> | <br /> | <br /> |}<br /> <br /> == Week 5 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ffffdd;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 5-1<br /> | 27-Sept-2012<br /> | <br /> | Graphical Interfaces and node.js<br /> | <br /> | <br /> |-<br /> | 5-2<br /> | 28<br /> | <br /> | Lab Time<br /> | <br /> |<br /> |-<br /> | 5-3<br /> | 1-Oct-2012<br /> | 2.1-2.3.5, 3.2.13<br /> | Booting, Memory Map, Cross-Development, Processor Basics, TI ARM<br /> | <br /> | <br /> |-<br /> | 5-4<br /> | 2<br /> | 4.1-4.3.3<br /> | The Kernel<br /> | <br /> | [[EBC Exercise 22 Cross-Compiling]]<br /> |}<br /> <br /> == Week 6 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ffddff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 6-1<br /> | 4<br /> | 4.4-4.5, 5.1-5.2<br /> | Adding to the Kernel makefile, Kernel Initialization<br /> | Find the Beagle version of Figure 2-5 on page 25. Be sure to find a numeric value for the starting address of the POP SDRAM. Note where you found this information.<br /> | [[EBC Exercise 23 Configuring the Kernel]]<br /> |-<br /> | &quot;<br /> | &quot;<br /> | 5.3-5.6<br /> | Command Line Processing, __setup Macro<br /> | Configuring the Kernel Lab<br /> | [[EBC Exercise 24 Kconfig Edits]]<br /> |-<br /> | 6-2<br /> | 5<br /> | <br /> | Lab Time<br /> | <br /> | <br /> |-<br /> | 6-3<br /> | 8<br /> | 6.1-6.3<br /> | System Initialization<br /> | Project Status Report, update your project status page.<br /> | [[EBC Exercise 21a Boot Sequence]]<br /> [[ECE497 Contributions and Project Status]]<br /> |-<br /> | 6-4<br /> | 9<br /> | 6.4-6.7<br /> | Initial RAM Disk, Using initramfs<br /> | <br /> | <br /> |}<br /> <br /> == Week 7 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ffffff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 7-1<br /> | 15<br /> | 7.1-7.3<br /> | Bootloaders, Das U-Boot<br /> | <br /> | [[EBC Exercise 25 Configuring U-boot]]<br /> |-<br /> | 7-2<br /> | 16<br /> | <br /> | Demo and Work Day<br /> | <br /> | <br /> |-<br /> | 7-3<br /> | 18<br /> | 8.1-8.4<br /> | Device Driver Basics, Driver Methods<br /> | <br /> | [[EBC Exercise 08 Installing Development Tools]]<br /> [[EBC Exercise 26 Device Drivers]]<br /> |-<br /> | 7-4<br /> | 19<br /> | 11.1-11.4<br /> | BusyBox<br /> | In B105<br /> | [[EBC Exercise 27 BusyBox]]<br /> <br /> |}<br /> <br /> == Week 8 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ddffff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 8-1<br /> | 22<br /> | [http://gstreamer.freedesktop.org/ GStreamer]<br /> | GStreamer ([http://wiki.oz9aec.net/index.php/Gstreamer_cheat_sheet Cheat Sheet],<br /> [http://www.oz9aec.net/index.php/gstreamer/345-a-weekend-with-gstreamer Weekend with GStreamer])<br /> | Status Report<br /> | [[EBC Exercise 29 GStreamer]] (optional)<br /> |-<br /> | 8-2<br /> | 23<br /> |<br /> | <br /> | Project Time<br /> | <br /> |-<br /> | 8-3<br /> | 25<br /> | <br /> | Remote debugging with gdb, cbrowser/cscope and strace<br /> | Project Time<br /> | [[EBC Exercise 28 Remote gdb and more]] (optional)<br /> |-<br /> | 8-4<br /> | 26<br /> | <br /> | Project Time<br /> | <br /> | [[ECE497 Contributions and Project Status]]<br /> |}<br /> <br /> == Week 9 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ffffff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 9-1<br /> | 29<br /> | <br /> | Project Time all week<br /> | <br /> | <br /> |-<br /> | 9-2<br /> | 30<br /> | <br /> | <br /> | <br /> | <br /> |-<br /> | 9-3<br /> | 1-Nov-2012<br /> | <br /> | <br /> | <br /> | <br /> |-<br /> | 9-4<br /> | 2<br /> |<br /> | <br /> |<br /> |<br /> |}<br /> <br /> == Week 10 ==<br /> <br /> {| style=&quot;color:blue; background-color:#ffffff;&quot; cellpadding=&quot;10&quot; cellspacing=&quot;0&quot; border=&quot;1&quot;<br /> ! Day !! Date !! Reading !! Topic !! Exercise !! Links<br /> |-<br /> | 10-1<br /> | 5<br /> | <br /> | <br /> | Project Time all week<br /> | <br /> |-<br /> | 10-2<br /> | 6<br /> | <br /> | <br /> | <br /> | <br /> |-<br /> | 10-3<br /> | 8<br /> | <br /> | <br /> | <br /> | <br /> |-<br /> | 10-4<br /> | 9<br /> |<br /> | <br /> | Cathy Wicks?<br /> |<br /> |}<br /> <br /> {{YoderFoot}}</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T03:35:54Z

<p>Richarsm: /* Code */</p> <hr /> <div>[[Category:ECE497]]<br /> [[Category:Adafruit]]<br /> <br /> The offical page can be found at [http://adafruit.com/products/306 Digital Addressable RGB LED w/ PWM waterproof flexi strip]<br /> <br /> [[File:digitalledstrip_LRG.jpg|200px|thumb|left|LPD8806]]<br /> <br /> == Introduction ==<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.<br /> <br /> == Code ==<br /> <br /> https://github.com/adammhaile/RPi-LPD8806<br /> <br /> https://github.com/Sh4d/LPD8806<br /> <br /> http://www.kernel.org/doc/Documentation/spi/spidev_test.c<br /> <br /> == Troubleshooting ==<br /> <br /> When I got the LED strip, it did not work as expected. Only the first two lights would stay lit and would only change based on random values that they would get when initialized with noise. After reading this thread on the Adafruit forums http://forums.adafruit.com/viewtopic.php?t=32825 we were able to get a working strip of LEDs.</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T03:07:39Z

<p>Richarsm: Added categories</p> <hr /> <div>[[Category:ECE497]]<br /> [[Category:Adafruit]]<br /> <br /> The offical page can be found at [http://adafruit.com/products/306 Digital Addressable RGB LED w/ PWM waterproof flexi strip]<br /> <br /> [[File:digitalledstrip_LRG.jpg|200px|thumb|left|LPD8806]]<br /> <br /> == Introduction ==<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.<br /> <br /> == Code ==<br /> <br /> https://github.com/adammhaile/RPi-LPD8806<br /> https://github.com/Sh4d/LPD8806<br /> <br /> == Troubleshooting ==<br /> <br /> When I got the LED strip, it did not work as expected. Only the first two lights would stay lit and would only change based on random values that they would get when initialized with noise. After reading this thread on the Adafruit forums http://forums.adafruit.com/viewtopic.php?t=32825 we were able to get a working strip of LEDs.</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T03:07:06Z

<p>Richarsm: Richarsm moved page Adafruit LPD8806 to Adafruit: LED Strip LPD8806: formatting</p> <hr /> <div>The offical page can be found at [http://adafruit.com/products/306 Digital Addressable RGB LED w/ PWM waterproof flexi strip]<br /> <br /> <br /> [[File:digitalledstrip_LRG.jpg|200px|thumb|left|LPD8806]]<br /> <br /> <br /> <br /> == Introduction ==<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.<br /> <br /> == Code ==<br /> <br /> https://github.com/adammhaile/RPi-LPD8806<br /> https://github.com/Sh4d/LPD8806<br /> <br /> == Troubleshooting ==<br /> <br /> When I got the LED strip, it did not work as expected. Only the first two lights would stay lit and would only change based on random values that they would get when initialized with noise. After reading this thread on the Adafruit forums http://forums.adafruit.com/viewtopic.php?t=32825 we were able to get a working strip of LEDs.</div>

Richarsm http://elinux.org/Adafruit_LPD8806 2012-11-05T03:07:06Z

<p>Richarsm: Richarsm moved page Adafruit LPD8806 to Adafruit: LED Strip LPD8806: formatting</p> <hr /> <div>#REDIRECT [[Adafruit: LED Strip LPD8806]]</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T02:57:14Z

<p>Richarsm: added subsections and code</p> <hr /> <div>The offical page can be found at [http://adafruit.com/products/306 Digital Addressable RGB LED w/ PWM waterproof flexi strip]<br /> <br /> <br /> [[File:digitalledstrip_LRG.jpg|200px|thumb|left|LPD8806]]<br /> <br /> <br /> <br /> == Introduction ==<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.<br /> <br /> == Code ==<br /> <br /> https://github.com/adammhaile/RPi-LPD8806<br /> https://github.com/Sh4d/LPD8806<br /> <br /> == Troubleshooting ==<br /> <br /> When I got the LED strip, it did not work as expected. Only the first two lights would stay lit and would only change based on random values that they would get when initialized with noise. After reading this thread on the Adafruit forums http://forums.adafruit.com/viewtopic.php?t=32825 we were able to get a working strip of LEDs.</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T02:46:13Z

<p>Richarsm: </p> <hr /> <div>The offical page can be found at [http://adafruit.com/products/306 Digital Addressable RGB LED w/ PWM waterproof flexi strip]<br /> <br /> <br /> [[File:digitalledstrip_LRG.jpg|200px|thumb|left|LPD8806]]<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T02:45:58Z

<p>Richarsm: </p> <hr /> <div>The offical page can be found at [http://adafruit.com/products/306 Adafruit &quot;Digital Addressable RGB LED w/ PWM waterproof flexi strip&quot;]<br /> <br /> <br /> [[File:digitalledstrip_LRG.jpg|200px|thumb|left|LPD8806]]<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T02:45:25Z

<p>Richarsm: </p> <hr /> <div>The offical page can be found at [http://adafruit.com/products/306 Adafruit &quot;Digital Addressable RGB LED w/ PWM waterproof flexi strip&quot;]<br /> <br /> <br /> [[File:digitalledstrip_LRG.jpg|200px|thumb|left|alt text]]<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T02:45:02Z

<p>Richarsm: </p> <hr /> <div>The offical page can be found at [http://adafruit.com/products/306 Adafruit &quot;Digital Addressable RGB LED w/ PWM waterproof flexi strip&quot;]<br /> <br /> <br /> [[File:http://www.adafruit.com/images/large/digitalledstrip_LRG.jpg|200px|thumb|left|alt text]]<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.</div>

Richarsm http://elinux.org/Adafruit:_LED_Strip_LPD8806 2012-11-05T02:44:07Z

<p>Richarsm: </p> <hr /> <div>Adafruit LPD8806<br /> http://adafruit.com/products/306<br /> <br /> [[File:http://www.adafruit.com/images/large/digitalledstrip_LRG.jpg|200px|thumb|left|alt text]]<br /> <br /> This is an LED strip housed in waterproof material with 32 LEDs per meter. The LEDs are controlled by shift registers using LPD8806 controller that controls two LEDs at a time with pulse width modulation. This chip has built in 1.2 MHz high speed 7-bit PWM for each channel which relates to 21-bit color. At each end is a 4-pin JST connector which is sealed in the 5 meter version. This needs to be powered by a 5V power source and should not go above 5.5V.</div>

Richarsm http://elinux.org/File:Digitalledstrip_LRG.jpg 2012-11-05T02:43:10Z

<p>Richarsm: </p> <hr /> <div></div>

Richarsm http://elinux.org/ECE497_richarsm_Project 2012-11-05T02:42:12Z

<p>Richarsm: Richarsm moved page ECE497 richarsm Project to Adafruit LPD8806: Make it so it's more generic.</p> <hr /> <div>#REDIRECT [[Adafruit LPD8806]]</div>

Richarsm