; OCD Commander dump of board configuration registers ; Configuration logged after warm reset, before running *any* code ; (warm reset being the OCD Commander reset command) >endian big BIG Endian set for WORD and DASM commands >dcr 0x018 ; 0x018: OCM0_ISARC R/W OCM Instruction-Side Address Range Compare DCR24 0C000000 >dcr 0x019 ; 0x019: OCM0_ISCNTL R/W OCM Instruction-Side Control Register DCR25 40000000 >dcr 0x01A ; 0x01A: OCM0_DSARC R/W OCM Data-Side Address Range Compare Register DCR26 74000000 >dcr 0x01B ; 0x01B: OCM0_DSCNTL R/W OCM Data-Side Control Register DCR27 40000000 >dcr 0x084 ; 0x084: PLB0_BESR R/Clear PLB Bus Error Status Register DCR132 00000000 >dcr 0x086 ; 0x086: PLB0_BEAR R PLB Bus Error Address Register DCR134 3F600300 >dcr 0x087 ; 0x087: PLB0_ACR R/W PLB Arbiter Control Register DCR135 00000000 >dcr 0x0A0 ; 0x0A0: POB0_BESR0 R/Clear PLB to OPB Bus Error Status Register 0 DCR160 00000000 >dcr 0x0A2 ; 0x0A2: POB0_BEAR R PLB to OPB Bus Error Address Register DCR162 EF600604 >dcr 0x0A4 ; 0x0A4: POB0_BESR1 R/Clear PLB to OPB Bus Error Status Register 1 DCR164 00000000 >dcr 0x0B0 ; 0x0B0: CPC0_PLLMR R PLL Mode Register DCR176 A4B6A000 >dcr 0x0B1 ; 0x0B1: CPC0_CR0 R/W Chip Control Register 0 DCR177 0000003C >dcr 0x0B2 ; 0x0B2: CPC0_CR1 R/W Chip Control Register 1 DCR178 2B0DB800 >dcr 0x0B4 ; 0x0B4: CPC0_PSR R Chip Pin Strapping Register DCR180 5BA81400 >dcr 0x0B5 ; 0x0B5: CPC0_JTAGID R JTAG ID Register DCR181 42050049 >dcr 0x0B8 ; 0x0B8: CPC0_SR R CPM Status Register DCR184 FFFFFFFF >dcr 0x0B9 ; 0x0B9: CPC0_ER R/W CPM Enable Register DCR185 00000000 >dcr 0x0BA ; 0x0BA: CPC0_FR R/W CPM Force Register DCR186 00000000 >dcr 0x0C0 ; 0x0C0: UIC0_SR R/Clear UIC0 Status Register DCR192 00000060 >dcr 0x0C2 ; 0x0C2: UIC0_ER R/W UIC0 Enable Register DCR194 00000000 >dcr 0x0C3 ; 0x0C3: UIC0_CR R/W UIC0 Critical Register DCR195 00000020 >dcr 0x0C4 ; 0x0C4: UIC0_PR R/W UIC0 Polarity Register DCR196 FFFFFFE0 >dcr 0x0C5 ; 0x0C5: UIC0_TR R/W UIC0 Triggering Register DCR197 10000000 >dcr 0x0C6 ; 0x0C6: UIC0_MSR R UIC0 Masked Status Register DCR198 00000000 >dcr 0x0C7 ; 0x0C7: UIC0_VR R UIC0 Vector Register DCR199 00000000 >dcr 0x0C8 ; 0x0C8: UIC0_VCR W UIC0 Vector Configuration Register DCR200 00000060 >dcr 0x100 ; 0x100: DMA0_CR0 R/W DMA Channel Control Register 0 DCR256 00000000 >dcr 0x101 ; 0x101: DMA0_CT0 R/W DMA Count Register 0 DCR257 00000000 >dcr 0x102 ; 0x102: DMA0_DA0 R/W DMA Destination Address Register 0 DCR258 00000000 >dcr 0x103 ; 0x103: DMA0_SA0 R/W DMA Source Address Register 0 DCR259 00000000 >dcr 0x104 ; 0x104: DMA0_SG0 R/W DMA Scatter/Gather Descriptor Address Register 0 DCR260 00000000 >dcr 0x108 ; 0x108: DMA0_CR1 R/W DMA Channel Control Register 1 DCR264 00000000 >dcr 0x109 ; 0x109: DMA0_CT1 R/W DMA Count Register 1 DCR265 00000000 >dcr 0x10A ; 0x10A: DMA0_DA1 R/W DMA Destination Address Register 1 DCR266 00000000 >dcr 0x10B ; 0x10B: DMA0_SA1 R/W DMA Source Address Register 1 DCR267 00000000 >dcr 0x10C ; 0x10C: DMA0_SG1 R/W DMA Scatter/Gather Descriptor Address Register 1 DCR268 00000000 >dcr 0x110 ; 0x110: DMA0_CR2 R/W DMA Channel Control Register 2 DCR272 00000000 >dcr 0x111 ; 0x111: DMA0_CT2 R/W DMA Count Register 2 DCR273 00000000 >dcr 0x112 ; 0x112: DMA0_DA2 R/W DMA Destination Address Register 2 DCR274 00000000 >dcr 0x113 ; 0x113: DMA0_SA2 R/W DMA Source Address Register 2 DCR275 00000000 >dcr 0x114 ; 0x114: DMA0_SG2 R/W DMA Scatter/Gather Descriptor Address Register 2 DCR276 00000000 >dcr 0x118 ; 0x118: DMA0_CR3 R/W DMA Channel Control Register 3 DCR280 00000000 >dcr 0x119 ; 0x119: DMA0_CT3 R/W DMA Count Register 3 DCR281 00000000 >dcr 0x11A ; 0x11A: DMA0_DA3 R/W DMA Destination Address Register 3 DCR282 00000000 >dcr 0x11B ; 0x11B: DMA0_SA3 R/W DMA Source Address Register 3 DCR283 00000000 >dcr 0x11C ; 0x11C: DMA0_SG3 R/W DMA Scatter/Gather Descriptor Address DCR284 00000000 >dcr 0x120 ; 0x120: DMA0_SR R/Clear DMA Status Register DCR288 00000000 >dcr 0x123 ; 0x123: DMA0_SGC R/W DMA Scatter/Gather Command Register DCR291 00000000 >dcr 0x125 ; 0x125: DMA0_SLP R/W DMA Sleep Mode Register DCR293 07C00000 >dcr 0x126 ; 0x126: DMA0_POL R/W DMA Polarity Configuration Register DCR294 00000000 >dcr 0x180 ; 0x180: MAL0_CFG R/W MAL Configuration Register DCR384 0007C000 >dcr 0x181 ; 0x181: MAL0_ESR R/Clear Error Status Register DCR385 00000000 >dcr 0x182 ; 0x182: MAL0_IER R/W Interrupt Enable Register DCR386 00000000 >dcr 0x184 ; 0x184: MAL0_TXCASR R/W Tx Channel Active Register (Set) DCR388 00000000 >dcr 0x185 ; 0x185: MAL0_TXCARR R/W Tx Channel Active Register (Reset) DCR389 00000000 >dcr 0x186 ; 0x186: MAL0_TXEOBISR R/Clear Tx End of Buffer Interrupt Status Register DCR390 00000000 >dcr 0x187 ; 0x187: MAL0_TXDEIR R/Clear Tx Descriptor Error Interrupt Register DCR391 00000000 >dcr 0x190 ; 0x190: MAL0_RXCASR R/W Rx Channel Active Register (Set) DCR400 00000000 >dcr 0x191 ; 0x191: MAL0_RXCARR R/W Rx Channel Active Register (Reset) DCR401 00000000 >dcr 0x192 ; 0x192: MAL0_RXEOBISR R/Clear Rx End of Buffer Interrupt Status Register DCR402 00000000 >dcr 0x193 ; 0x193: MAL0_RXDEIR R/Clear Rx Descriptor Error Interrupt Register DCR403 00000000 >dcr 0x1A0 ; 0x1A0: MAL0_TXCTP0R R/W Channel Tx 0 Channel Table Pointer Register DCR416 00000000 >dcr 0x1A1 ; 0x1A1: MAL0_TXCTP1R R/W Channel Tx 1 Channel Table Pointer Register DCR417 00000000 >dcr 0x1E0 ; 0x1E0: MAL0_RCBS0 R/W Channel RX 0 Channel Buffer Size Register DCR480 00000000 >dcr 0x010 = 0x00 >dcr 0x11 ; offset 0x00: SDRAM0_BESR0 R/Clear Bus Error Syndrome Register 0 DCR17 00000000 >dcr 0x010 = 0x08 >dcr 0x11 ; offset 0x08: SDRAM0_BESR1 R/Clear Bus Error Syndrome Register 1 DCR17 00000000 >dcr 0x010 = 0x10 >dcr 0x11 ; offset 0x10: SDRAM0_BEAR R/W Bus Error Address Register DCR17 00000000 >dcr 0x010 = 0x20 >dcr 0x11 ; offset 0x20: SDRAM0_CFG R/W Memory Controller Options 1 DCR17 00800000 >dcr 0x010 = 0x30 >dcr 0x11 ; offset 0x30: SDRAM0_RTR R/W Refresh Timer Register DCR17 05F00000 >dcr 0x010 = 0x34 >dcr 0x11 ; offset 0x34: SDRAM0_PMIT R/W Power Management Idle Timer DCR17 07C00000 >dcr 0x010 = 0x40 >dcr 0x11 ; offset 0x40: SDRAM0_B0CR R/W Memory Bank 0 Configuration Register DCR17 00000000 >dcr 0x010 = 0x44 >dcr 0x11 ; offset 0x44: SDRAM0_B1CR R/W Memory Bank 1 Configuration Register DCR17 00000000 >dcr 0x010 = 0x48 >dcr 0x11 ; offset 0x48: SDRAM0_B2CR R/W Memory Bank 2 Configuration Register DCR17 00000000 >dcr 0x010 = 0x4C >dcr 0x11 ; offset 0x4C: SDRAM0_B3CR R/W Memory Bank 3 Configuration Register DCR17 00000000 >dcr 0x010 = 0x50 >dcr 0x11 ; offset 0x50: SDRAM0_B4CR R/W Memory Bank 4 Configuration Register DCR17 00000000 >dcr 0x010 = 0x54 >dcr 0x11 ; offset 0x54: SDRAM0_B5CR R/W Memory Bank 5 Configuration Register DCR17 00000000 >dcr 0x010 = 0x58 >dcr 0x11 ; offset 0x58: SDRAM0_B6CR R/W Memory Bank 6 Configuration Register DCR17 00000000 >dcr 0x010 = 0x5C >dcr 0x11 ; offset 0x5C: SDRAM0_B7CR R/W Memory Bank 7 Configuration Register DCR17 00000000 >dcr 0x010 = 0x80 >dcr 0x11 ; offset 0x80: SDRAM0_TR R/W SDRAM Timing Register 1 DCR17 00854009 >dcr 0x010 = 0x94 >dcr 0x11 ; offset 0x94: SDRAM0_ECCCFG R/W ECC Configuration DCR17 00000000 >dcr 0x010 = 0x98 >dcr 0x11 ; offset 0x98: SDRAM0_ECCESR R/Clear ECC Error Status Register DCR17 00000000 >dcr 0x012 = 0x00 >dcr 0x13 ; offset 0x00: EBC0_B0CR R/W Peripheral Bank 0 Configuration Register DCR19 FFE28000 >dcr 0x012 = 0x01 >dcr 0x13 ; offset 0x01: EBC0_B1CR R/W Peripheral Bank 1 Configuration Register DCR19 00000000 >dcr 0x012 = 0x02 >dcr 0x13 ; offset 0x02: EBC0_B2CR R/W Peripheral Bank 2 Configuration Register DCR19 00000000 >dcr 0x012 = 0x03 >dcr 0x13 ; offset 0x03: EBC0_B3CR R/W Peripheral Bank 3 Configuration Register DCR19 00000000 >dcr 0x012 = 0x04 >dcr 0x13 ; offset 0x04: EBC0_B4CR R/W Peripheral Bank 4 Configuration Register DCR19 00000000 >dcr 0x012 = 0x05 >dcr 0x13 ; offset 0x05: EBC0_B5CR R/W Peripheral Bank 5 Configuration Register DCR19 00000000 >dcr 0x012 = 0x06 >dcr 0x13 ; offset 0x06: EBC0_B6CR R/W Peripheral Bank 6 Configuration Register DCR19 00000000 >dcr 0x012 = 0x07 >dcr 0x13 ; offset 0x07: EBC0_B7CR R/W Peripheral Bank 7 Configuration Register DCR19 00000000 >dcr 0x012 = 0x10 >dcr 0x13 ; offset 0x10: EBC0_B0AP R/W Peripheral Bank 0 Access Parameters DCR19 7F8FFE80 >dcr 0x012 = 0x11 >dcr 0x13 ; offset 0x11: EBC0_B1AP R/W Peripheral Bank 1 Access Parameters DCR19 00000000 >dcr 0x012 = 0x12 >dcr 0x13 ; offset 0x12: EBC0_B2AP R/W Peripheral Bank 2 Access Parameters DCR19 00000000 >dcr 0x012 = 0x13 >dcr 0x13 ; offset 0x13: EBC0_B3AP R/W Peripheral Bank 3 Access Parameters DCR19 00000000 >dcr 0x012 = 0x14 >dcr 0x13 ; offset 0x14: EBC0_B4AP R/W Peripheral Bank 4 Access Parameters DCR19 00000000 >dcr 0x012 = 0x15 >dcr 0x13 ; offset 0x15: EBC0_B5AP R/W Peripheral Bank 5 Access Parameters DCR19 00000000 >dcr 0x012 = 0x16 >dcr 0x13 ; offset 0x16: EBC0_B6AP R/W Peripheral Bank 6 Access Parameters DCR19 00000000 >dcr 0x012 = 0x17 >dcr 0x13 ; offset 0x17: EBC0_B7AP R/W Peripheral Bank 7 Access Parameters DCR19 00000000 >dcr 0x012 = 0x20 >dcr 0x13 ; offset 0x20: EBC0_BEAR R/W Peripheral Bus Error Address Register DCR19 00000000 >dcr 0x012 = 0x21 >dcr 0x13 ; offset 0x21: EBC0_BESR0 R/W Peripheral Bus Error Status Register 0 DCR19 00000000 >dcr 0x012 = 0x22 >dcr 0x13 ; offset 0x22: EBC0_BESR1 R/W Peripheral Bus Error Status Register 1 DCR19 00000000 >dcr 0x012 = 0x23 >dcr 0x13 ; offset 0x23: EBC0_CFG R/W External Peripheral Control Register DCR19 80400000 >word 0xEF400000 ; 0xEF400000: PCIL0_PMM0LA R/W PMM 0 Local Address EF400000: 0000FEFF >word 0xEF400004 ; 0xEF400004: PCIL0_PMM0MA R/W PMM 0 Mask/Attribute EF400004: 00000000 >word 0xEF400008 ; 0xEF400008: PCIL0_PMM0PCILA R/W PMM 0 PCI Low Address EF400008: 0000FEFF >word 0xEF40000C ; 0xEF40000C: PCIL0_PMM0PCIHA R/W PMM 0 PCI High Address EF40000C: 00000000 >word 0xEF400010 ; 0xEF400010: PCIL0_PMM1LA R/W PMM 1 Local Address EF400010: 000000A0 >word 0xEF400014 ; 0xEF400014: PCIL0_PMM1MA R/W PMM 1 Mask/Attribute EF400014: 00000000 >word 0xEF400018 ; 0xEF400018: PCIL0_PMM1PCILA R/W PMM 1 PCI Low Address EF400018: 00000000 >word 0xEF40001C ; 0xEF40001C: PCIL0_PMM1PCIHA R/W PMM 1 PCI High Address EF40001C: 00000000 >word 0xEF400020 ; 0xEF400020: PCIL0_PMM2LA R/W PMM 2 Local Address EF400020: 00000000 >word 0xEF400024 ; 0xEF400024: PCIL0_PMM2MA R/W PMM 2 Mask/Attribute EF400024: 00000000 >word 0xEF400028 ; 0xEF400028: PCIL0_PMM2PCILA R/W PMM 2 PCI Low Address EF400028: 00000000 >word 0xEF40002C ; 0xEF40002C: PCIL0_PMM2PCIHA R/W PMM 2 PCI High Address EF40002C: 00000000 >word 0xEF400030 ; 0xEF400030: PCIL0_PTM1MS R/W PTM 1 Memory Size EF400030: 01000080 >word 0xEF400034 ; 0xEF400034: PCIL0_PTM1LA R/W PTM 1 Local Address EF400034: 00000000 >word 0xEF400038 ; 0xEF400038: PCIL0_PTM2MS R/W PTM 2 Memory Size EF400038: 00000000 >word 0xEF40003C ; 0xEF40003C: PCIL0_PTM2LA R/W PTM 2 Local Address Serial Ports EF40003C: 00000000 >byte 0xEF600300 ; 0xEF600300: UART0_RBR R UART 0 Receiver Buffer Register Note:Set UART0_LCR[DLAB] = 0 to access. EF600300: 0D >byte 0xEF600301 ; 0xEF600301: UART0_IER R/W UART 0 Interrupt Enable Register Note:Set UART0_LCR[DLAB] = 0 to access. EF600301: 00 >byte 0xEF600302 ; 0xEF600302: UART0_IIR R UART 0 Interrupt Identification Register EF600302: 01 >byte 0xEF600303 ; 0xEF600303: UART0_LCR R/W UART 0 Line Control Register EF600303: 00 >byte 0xEF600304 ; 0xEF600304: UART0_MCR R/W UART 0 Modem Control Register EF600304: 00 >byte 0xEF600305 ; 0xEF600305: UART0_LSR R/W UART 0 Line Status Register EF600305: 60 >byte 0xEF600306 ; 0xEF600306: UART0_MSR R/W UART 0 Modem Status Register EF600306: 20 >byte 0xEF600307 ; 0xEF600307: UART0_SCR R/W UART 0 Scratch Register EF600307: 00 >byte 0xEF600303 = 0x83 ; set UART0_LCR[DLAB] bit to read hidden regs >half 0xEF600300 ; 0xEF600300: UART0_DLL R/W UART 0 Baud-rate Divisor Latch LSB Note:Set UART0_LCR[DLAB] = 1 to access. EF600300: 0000 >byte 0xEF600301 ; 0xEF600301: UART0_DLM R/W UART 0 Baud-rate Divisor Latch MSB Note:Set UART0_LCR[DLAB] = 1 to access. EF600301: 00 >byte 0xEF600303 = 0x03 ; unset UART0_LCR[DLAB] bit to read regular regs (8 data bits) >byte 0xEF600400 ; 0xEF600400: UART1_RBR R UART 1 Receiver Buffer Register Note:Set UART1_LCR[DLAB] = 0 to access. EF600400: 02 >byte 0xEF600401 ; 0xEF600401: UART1_IER R/W UART 1 Interrupt Enable Register Note:Set UART1_LCR[DLAB] = 0 to access. EF600401: 00 >byte 0xEF600402 ; 0xEF600402: UART1_IIR R UART 1 Interrupt Identification Register EF600402: 01 >byte 0xEF600403 ; 0xEF600403: UART1_LCR R/W UART 1 Line Control Register EF600403: 00 >byte 0xEF600404 ; 0xEF600404: UART1_MCR R/W UART 1 Modem Control Register EF600404: 00 >byte 0xEF600405 ; 0xEF600405: UART1_LSR R/W UART 1 Line Status Register EF600405: 60 >byte 0xEF600406 ; 0xEF600406: UART1_MSR R/W UART 1 Modem Status Register EF600406: 00 >byte 0xEF600407 ; 0xEF600407: UART1_SCR R/W UART 1 Scratch Register EF600407: 00 >byte 0xEF600403 = 0x83 ; set UART1_LCR[DLAB] bit to read hidden regs >half 0xEF600400 ; 0xEF600400: UART1_DLL R/W UART 1 Baud-rate Divisor Latch LSB Note:Set UART1_LCR[DLAB] = 1 to access. EF600400: 0000 >byte 0xEF600401 ; 0xEF600401: UART1_DLM R/W UART 1 Baud-rate Divisor Latch MSB Note:Set UART1_LCR[DLAB] = 1 to access. EF600401: 00 >byte 0xEF600403 = 0x03 ; unset UART1_LCR[DLAB] bit to read regular regs (8 data bits) >byte 0xEF600500 ; 0xEF600500: IIC0_MDBUF R/W IIC0 Master Data Buffer EF600500: 00 >byte 0xEF600502 ; 0xEF600502: IIC0_SDBUF R/W IIC0 Slave Data Buffer EF600502: 00 >byte 0xEF600504 ; 0xEF600504: IIC0_LMADR R/W IIC0 Low Master Address EF600504: A1 >byte 0xEF600505 ; 0xEF600505: IIC0_HMADR R/W IIC0 High Master Address EF600505: 00 >byte 0xEF600506 ; 0xEF600506: IIC0_CNTL R/W IIC0 Control EF600506: 00 >byte 0xEF600507 ; 0xEF600507: IIC0_MDCNTL R/W IIC0 Mode Control EF600507: 00 >byte 0xEF600508 ; 0xEF600508: IIC0_STS R/W IIC0 Status EF600508: 00 >byte 0xEF600509 ; 0xEF600509: IIC0_EXTSTS R/W IIC0 Extended Status EF600509: 60 >byte 0xEF60050A ; 0xEF60050A: IIC0_LSADR R/W IIC0 Low Slave Address EF60050A: 00 >byte 0xEF60050B ; 0xEF60050B: IIC0_HSADR R/W IIC0 High Slave Address EF60050B: 00 >byte 0xEF60050C ; 0xEF60050C: IIC0_CLKDIV R/W IIC0 Clock Divide EF60050C: 00 >byte 0xEF60050D ; 0xEF60050D: IIC0_INTRMSK R/W IIC0 Interrupt Mask EF60050D: 00 >byte 0xEF60050E ; 0xEF60050E: IIC0_XFRCNT R/W IIC0 Transfer Count EF60050E: 00 >byte 0xEF60050F ; 0xEF60050F: IIC0_XTCNTLSS R/W IIC0 Extended Control and Slave Status EF60050F: 00 >byte 0xEF600510 ; 0xEF600510: IIC0_DIRECTCNTL R/W IIC0 Direct Control EF600510: 0F >byte 0xEF600600 ; 0xEF600600: OPBA0_PR R/W OPB Arbiter Priority Register EF600600: 1B >byte 0xEF600601 ; 0xEF600601: OPBA0_CR R/W OPB Arbiter Control Register EF600601: 00 >word 0xEF600700 ; 0xEF600700: GPIO0_OR R/W GPIO0 Output Register EF600700: 00000000 >word 0xEF600704 ; 0xEF600704: GPIO0_TCR R/W GPIO0 Three-State Control Register EF600704: 00000000 >word 0xEF600718 ; 0xEF600718: GPIO0_ODR R/W GPIO0 Open Drain Register EF600718: 00000000 >word 0xEF60071C ; 0xEF60071C: GPIO0_IR R GPIO0 Input Register EF60071C: 2FFFFF00 >word 0xEF600800 ; 0xEF600800: EMAC0_MR0 R/W Mode Register 0 EF600800: C0000000 >word 0xEF600804 ; 0xEF600804: EMAC0_MR1 R/W Mode Register 1 EF600804: 00000000 >word 0xEF600808 ; 0xEF600808: EMAC0_TMR0 R/W Transmit Mode Register 0 EF600808: 00000000 >word 0xEF60080C ; 0xEF60080C: EMAC0_TMR1 R/W Transmit Mode Register 1 EF60080C: 380F0000 >word 0xEF600810 ; 0xEF600810: EMAC0_RMR R/W Receive Mode Register EF600810: 00000000 >word 0xEF600814 ; 0xEF600814: EMAC0_ISR R/W Interrupt Status Register EF600814: 00000000 >word 0xEF600818 ; 0xEF600818: EMAC0_ISER R/W Interrupt Status Enable Register EF600818: 00000000 >word 0xEF60081C ; 0xEF60081C: EMAC0_IAHR R/W Individual Address High EF60081C: 00000000 >word 0xEF600820 ; 0xEF600820: EMAC0_IALR R/W Individual Address Low EF600820: 00000000 >word 0xEF600824 ; 0xEF600824: EMAC0_VTPID R/W VLAN TPID Register EF600824: 00008808 >word 0xEF600828 ; 0xEF600828: EMAC0_VTCI R/W VLAN TCI Register EF600828: 00000000 >word 0xEF60082C ; 0xEF60082C: EMAC0_PTR R/W Pause Timer Register EF60082C: 0000FFFF >word 0xEF600830 ; 0xEF600830: EMAC0_IAHT1 R/W Individual Address Hash Table 1 EF600830: 00000000 >word 0xEF600834 ; 0xEF600834: EMAC0_IAHT2 R/W Individual Address Hash Table 2 EF600834: 00000000 >word 0xEF600838 ; 0xEF600838: EMAC0_IAHT3 R/W Individual Address Hash Table 3 EF600838: 00000000 >word 0xEF60083C ; 0xEF60083C: EMAC0_IAHT4 R/W Individual Address Hash Table 4 EF60083C: 00000000 >word 0xEF600840 ; 0xEF600840: EMAC0_GAHT1 R/W Group Address Hash Table 1 EF600840: 00000000 >word 0xEF600844 ; 0xEF600844: EMAC0_GAHT2 R/W Group Address Hash Table 2 EF600844: 00000000 >word 0xEF600848 ; 0xEF600848: EMAC0_GAHT3 R/W Group Address Hash Table 3 EF600848: 00000000 >word 0xEF60084C ; 0xEF60084C: EMAC0_GAHT4 R/W Group Address Hash Table 4 EF60084C: 00000000 >word 0xEF600850 ; 0xEF600850: EMAC0_LSAH R Last Source Address High EF600850: 00000000 >word 0xEF600854 ; 0xEF600854: EMAC0_LSAL R Last Source Address Low EF600854: 00000000 >word 0xEF600858 ; 0xEF600858: EMAC0_IPGVR R/W Inter-Packet Gap Value Register EF600858: 00000004 >word 0xEF60085C ; 0xEF60085C: EMAC0_STACR R/W STA Control Register EF60085C: 00008000 >word 0xEF600860 ; 0xEF600860: EMAC0_TRTR R/W Transmit Request Threshold Register EF600860: 00000000 >word 0xEF600864 ; 0xEF600864: EMAC0_RWMR R/W Receive Low/High Water Mark Register EF600864: 04001000 >word 0xEF600868 ; 0xEF600868: EMAC0_OCTX R/W Number of Octets Transmitted Register EF600868: 00000000 >word 0xEF60086C ; 0xEF60086C: EMAC0_OCRX R/W Number of Octets Received Register EF60086C: 00000000 >spr 0x3B3 ; CCR0 Core Configuration Register 0 947 0x3B3 0x27D Read/Write SPR947 00700000 >spr 0x009 ; CTR Count Register 9 0x009 0x120 Read/Write SPR9 FFFFFFFF >spr 0x3F6 ; DAC1 Data Address Compare 1 1014 0x3F6 0x2DF Read/Write SPR1014 00000800 >spr 0x3F7 ; DAC2 Data Address Compare 2 1015 0x3F7 0x2FF Read/Write SPR1015 80480000 >spr 0x3F2 ; DBCR0 Debug Control Register 0 1010 0x3F2 0x25F Read/Write SPR1010 00000000 >spr 0x3BD ; DBCR1 Debug Control Register 1 957 0x3BD 0x3BD Read/Write SPR957 00000000 >spr 0x3F0 ; DBSR Debug Status Register 1008 0x3F0 0x21F Read/Clear SPR1008 00000300 >spr 0x3FA ; DCCR Data Cache Cachability Register 1018 0x3FA 0x35F Read/Write SPR1018 00000000 >spr 0x3BA ; DCWR Data Cache Write-through Register 954 0x3BA 0x35D Read/Write SPR954 00000000 >spr 0x3B6 ; DVC1 Data Value Compare 1 950 0x3B6 0x2DD Read/Write SPR950 20048000 >spr 0x3B7 ; DVC2 Data Value Compare 2 951 0x3B7 0x2FD Read/Write SPR951 00000440 >spr 0x3D5 ; DEAR Data Error Address Register 981 0x3D5 0x2BE Read/Write SPR981 00000000 >spr 0x3D4 ; ESR Exception Syndrome Register 980 0x3D4 0x29E Read/Write SPR980 00000000 >spr 0x3D6 ; EVPR Exception Vector Prefix Register 982 0x3D6 0x2DE Read/Write SPR982 00000000 >spr 0x3F4 ; IAC1 Instruction Address Compare 1 1012 0x3F4 0x29F Read/Write SPR1012 75040000 >spr 0x3F5 ; IAC2 Instruction Address Compare 2 1013 0x3F5 0x2B5 Read/Write SPR1013 00138000 >spr 0x3B4 ; IAC3 Instruction Address Compare 3 948 0x3B4 0x29D Read/Write SPR948 110D0008 >spr 0x3B5 ; IAC4 Instruction Address Compare 4 949 0x3B5 0x2BD Read/Write SPR949 04008050 >spr 0x3FB ; ICCR Instruction Cache Cachability Register 1019 0x3FB 0x37F Read/Write SPR1019 00000000 >spr 0x3D3 ; ICDBDR Instruction Cache Debug Data Register 979 0x3D3 0x27E Read-only SPR979 54000000 >spr 0x008 ; LR Link Register 8 0x008 0x100 Read/Write SPR8 01FD32B8 >spr 0x3B1 ; PID Process ID 945 0x3B1 0x23D Read/Write SPR945 00000000 >spr 0x3DB ; PIT Programmable Interval Timer 987 0x3DB 0x37E Read/Write SPR987 00000000 >spr 0x11F ; PVR Processor Version Register 287 0x11F 0x3E8 Read-only SPR287 40110145 >spr 0x3B9 ; SGR Storage Guarded Register 953 0x3B9 0x33D Read/Write SPR953 FFFFFFFF >spr 0x3BB ; SLER Storage Little Endian Register 955 0x3BB 0x37D Read/Write SPR955 00000000 >spr 0x110 ; SPRG0 SPR General 0 272 0x110 0x208 Read/Write SPR272 00001000 >spr 0x111 ; SPRG1 SPR General 1 273 0x111 0x228 Read/Write SPR273 01FAEDD8 >spr 0x112 ; SPRG2 SPR General 2 274 0x112 0x248 Read/Write SPR274 00000000 >spr 0x113 ; SPRG3 SPR General 3 275 0x113 0x268 Read/Write SPR275 90900048 >spr 0x104 ; SPRG4 SPR General 4 260 0x104 0x088 Read-only SPR260 00000110 >spr 0x114 ; SPRG4 SPR General 4 276 0x114 0x288 Read/Write SPR276 00000110 >spr 0x105 ; SPRG5 SPR General 5 261 0x105 0x0A8 Read-only SPR261 88010000 >spr 0x115 ; SPRG5 SPR General 5 277 0x115 0x2A8 Read/Write SPR277 88010000 >spr 0x106 ; SPRG6 SPR General 6 262 0x106 0x0C8 Read-only SPR262 20200020 >spr 0x116 ; SPRG6 SPR General 6 278 0x116 0x2C8 Read/Write SPR278 20200020 >spr 0x107 ; SPRG7 SPR General 7 263 0x107 0x0E8 Read-only SPR263 00000402 >spr 0x117 ; SPRG7 SPR General 7 279 0x117 0x2E8 Read/Write SPR279 00000402 >spr 0x01A ; SRR0 Save/Restore Register 0 26 0x01A 0x340 Read/Write SPR26 01FD32B8 >spr 0x01B ; SRR1 Save/Restore Register 1 27 0x01B 0x360 Read/Write SPR27 00000000 >spr 0x3DE ; SRR2 Save/Restore Register 2 990 0x3DE 0x3DE Read/Write SPR990 01FD32B8 >spr 0x3DF ; SRR3 Save/Restore Register 3 991 0x3DF 0x3FE Read/Write SPR991 00000000 >spr 0x3BC ; SU0R Storage User-defined 0 Register 956 0x3BC 0x39D Read/Write SPR956 00000000 >spr 0x11C ; TBL Time Base Lower 284 0x11C 0x388 Write-only SPR284 A4B1482F >spr 0x11D ; TBU Time Base Upper 285 0x11D 0x3A8 Write-only SPR285 0000000C >spr 0x3DA ; TCR Timer Control Register 986 0x3DA 0x35E Read/Write SPR986 00000000 >spr 0x3D8 ; TSR Timer Status Register 984 0x3D8 0x31E Read/Clear SPR984 DC000000 >spr 0x100 ; USPRG0 User SPR General 0 256 0x100 0x008 Read/Write SPR256 000A0000 >spr 0x001 ; XER Fixed Point Exception Register 1 0x001 0x020 Read/Write SPR1 00000000 >spr 0x3B0 ; ZPR Zone Protection Register 944 0x3B0 0x21D Privileged SPR944 00000000 >log off