ARM926EJ-S - Revision history

Glenn: catspec Category:ARM processors

2008-02-10T19:23:33Z

catspec Category:ARM processors

Prpplague at 15:49, 7 November 2007

2007-11-07T15:49:50Z

Prpplague at 15:48, 7 November 2007

2007-11-07T15:48:20Z

Prpplague at 15:44, 7 November 2007

2007-11-07T15:44:05Z

New page

ARM926EJ-S
ARM926EJ-S Jazelle-enhanced macrocell

The ARM926EJ-STM fully synthesizable processor features a Jazelle technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces, memory management unit (MMU). It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for Multi-layer AHB based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution.

A hardened implementation of the ARM926EJ is now available from the ARM Processor Foundry Program and the DesignStart Program

ARM926EJ-S Pic

View larger image

Applications

* Next generation smart phones, communicators & PDA's
* 3G baseband and applications processor
* Platform OS based devices
* Digital still camera
* Audio and video decoding
* Automotive infotainment

Features

* 32/16-bit RISC architecture (ARMv5TEJ)
* 32-bit ARM instruction set for maximum performance and flexibility
* 16-bit Thumb instruction set for increased code density
* DSP instruction extensions and single cycle MAC
* ARM Jazelle technology
* MMU which supports operating systems including Symbian OS, Windows CE, Linux
* Flexible instruction and data cache sizes
* Instruction and data TCM interfaces with wait state support
* EmbeddedICE-RT logic for real-time debug
* Industry standard AMBA bus AHB interfaces
* ETM interface for Real-time trace capability with ETM9
* Optional MOVE Coprocessor delivers video encoding performance

Benefits

* Runs all major OSs and existing middleware
* Single chip MCU, DSP and Java solution
* Support for leading Java run-times
* High-efficiency Java bytecode execution
* Ultra-low Java power consumption
* Java JIT compiler performance without the disadvantages
* Jazelle support code has no increase in VM size
* Simple single-processor software structure, no need for software partitioning across MCUs
* Single development toolkit for reduced development costs and shorter development cycle time
* Multiple sourcing from industry-leading silicon vendors
* Code-compatible upward migration path through to the latest Cortex family of processors
* Process portable synthesizable design
* Excellent debug support for SoC designers
* Instruction set can be extended by the use of coprocessors
* ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.

← Older revision		Revision as of 19:23, 10 February 2008
Line 31:		Line 31:
	[http://www.arm.com Arm Ltd Web Site]		[http://www.arm.com Arm Ltd Web Site]

−	[[Category:~~Processors~~]]	+	[[Category:ARM processors]]

@@ Line 5: / Line 5: @@
-== Applications ==
+=== Applications ===
 * Next generation smart phones, communicators & PDA's
 * 3G baseband and applications processor
@@ Line 14: / Line 14: @@
-== Features ==
+=== Features ===
 * 32/16-bit RISC architecture (ARMv5TEJ)
 * 32-bit ARM instruction set for maximum performance and flexibility
@@ Line 27: / Line 27: @@
 * ETM interface for Real-time trace capability with ETM9
 * Optional MOVE Coprocessor delivers video encoding performance

@@ Line 1: / Line 1: @@
 The ARM926EJ-STM fully synthesizable processor features a Jazelle technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces, memory management unit (MMU). It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for Multi-layer AHB based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution.
@@ Line 7: / Line 4: @@
-    * 32/16-bit RISC architecture (ARMv5TEJ)
+== Applications ==
-    * 32-bit ARM instruction set for maximum performance and flexibility
+* Next generation smart phones, communicators & PDA's
-    * 16-bit Thumb instruction set for increased code density
+* 3G baseband and applications processor
-    * DSP instruction extensions and single cycle MAC
+* Platform OS based devices
-    * ARM Jazelle technology
+* Digital still camera
-    * MMU which supports operating systems including Symbian OS, Windows CE, Linux
+* Audio and video decoding
-    * Flexible instruction and data cache sizes
+* Automotive infotainment
-    * Instruction and data TCM interfaces with wait state support
-    * EmbeddedICE-RT logic for real-time debug
-    * Industry standard AMBA bus AHB interfaces
-    * ETM interface for Real-time trace capability with ETM9
-    * Optional MOVE Coprocessor delivers video encoding performance
-    * Runs all major OSs and existing middleware
+== Features ==
-    * Single chip MCU, DSP and Java solution
+* 32/16-bit RISC architecture (ARMv5TEJ)
-    * Support for leading Java run-times
+* 32-bit ARM instruction set for maximum performance and flexibility
-    * High-efficiency Java bytecode execution
+* 16-bit Thumb instruction set for increased code density
-    * Ultra-low Java power consumption
+* DSP instruction extensions and single cycle MAC
-    * Java JIT compiler performance without the disadvantages
+* ARM Jazelle technology
-    * Jazelle support code has no increase in VM size
+* MMU which supports operating systems including Symbian OS, Windows CE, Linux
-    * Simple single-processor software structure, no need for software partitioning across MCUs
+* Flexible instruction and data cache sizes
-    * Single development toolkit for reduced development costs and shorter development cycle time
+* Instruction and data TCM interfaces with wait state support
-    * Multiple sourcing from industry-leading silicon vendors
+* EmbeddedICE-RT logic for real-time debug
-    * Code-compatible upward migration path through to the latest Cortex family of processors
+* Industry standard AMBA bus AHB interfaces
-    * Process portable synthesizable design
+* ETM interface for Real-time trace capability with ETM9
-    * Excellent debug support for SoC designers
+* Optional MOVE Coprocessor delivers video encoding performance
-    * Instruction set can be extended by the use of coprocessors
-    * ARM-EDA Reference Methodology deliverables significantly reduce the time to generate a specific technology implementation of the core and to generate industry standard views and models.