https://elinux.org/index.php?title=Amdm37x.cfg&feed=atom&action=historyAmdm37x.cfg - Revision history2024-03-28T23:47:16ZRevision history for this page on the wikiMediaWiki 1.31.0https://elinux.org/index.php?title=Amdm37x.cfg&diff=127712&oldid=prevWmat: target config2012-05-08T18:24:55Z<p>target config</p>
<p><b>New page</b></p><div><syntaxhighlight code="tcl"><br />
#<br />
# Copyright (C) 2010-2011 by Karl Kurbjun<br />
# Copyright (C) 2009-2011 by Øyvind Harboe<br />
# Copyright (C) 2009 by David Brownell<br />
# Copyright (C) 2009 by Magnus Lundin<br />
#<br />
# TI AM/DM37x<br />
# http://www.ti.com/litv/pdf/sprugn4b<br />
#<br />
# This script is based on the AM3517 initialization. It should be considered<br />
# preliminary since it needs more complete testing and only the basic<br />
# operations work.<br />
#<br />
<br />
###############################################################################<br />
# User modifiable parameters<br />
###############################################################################<br />
<br />
# This script uses the variable CHIPTYPE to determine whether this is an AM35x<br />
# or DM37x target. If CHIPTYPE is not set it will error out.<br />
if { [info exists CHIPTYPE] } {<br />
<br />
if { [info exists CHIPNAME] } {<br />
set _CHIPNAME $CHIPNAME<br />
} else {<br />
set _CHIPNAME $CHIPTYPE<br />
}<br />
<br />
switch $CHIPTYPE {<br />
dm37x {<br />
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan<br />
set _JRC_TAPID "-expected-id 0x2b89102f -expected-id 0x1b89102f -expected-id 0x0b89102f"<br />
}<br />
am35x {<br />
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan<br />
set _JRC_TAPID "-expected-id 0x0b7ae02f"<br />
}<br />
default {<br />
error "ERROR: CHIPTYPE was set, but it was not set to a valid value. Acceptable values are \"dm37x\" or \"am35x\"."<br />
}<br />
}<br />
} else {<br />
error "ERROR: CHIPTYPE was not defined. Please set CHIPTYPE to \"am35x\" for the AM35x or \"dm37x\" for the DM37x series in the board configuration."<br />
}<br />
<br />
# Run the adapter at the fastest acceptable speed with the slowest possible<br />
# core clock.<br />
adapter_khz 10<br />
<br />
###############################################################################<br />
# JTAG setup<br />
# The OpenOCD commands are described in the TAP Declaration section<br />
# http://openocd.berlios.de/doc/html/TAP-Declaration.html<br />
###############################################################################<br />
<br />
# The AM/DM37x has an ICEpick module in it like many of TI's other devices. More<br />
# can be read about this module in sprugn4b under chapter 27: "Debug and<br />
# Emulation". The module is used to route the JTAG chain to the various<br />
# subsystems in the chip.<br />
source [find target/icepick.cfg]<br />
<br />
# The TAP order should be described from the TDO connection in OpenOCD to the<br />
# TDI pin. The OpenOCD FAQ describes this in more detail:<br />
# http://openocd.berlios.de/doc/html/FAQ.html<br />
<br />
# From SPRUGN4B CH27 the available secondary TAPs are in this order from TDO:<br />
#<br />
# Device | TAP number<br />
# ---------|------------<br />
# DAP | 3<br />
# Sequencer| 2 Note: The sequencer is an ARM968<br />
# DSP | 1<br />
# D2D | 0<br />
#<br />
# Right now the only secondary tap enabled is the DAP so the rest are left<br />
# undescribed.<br />
<br />
######<br />
# Start of Chain Description<br />
# The Secondary TAPs all have enable functions defined for use with the ICEpick<br />
# Only the DAP is enabled. The AM37xx does not have the Sequencer or DSP but<br />
# the TAP numbers for ICEpick do not change.<br />
#<br />
# TODO: A disable function should also be added.<br />
######<br />
<br />
# Secondary TAP: DAP is closest to the TDO output<br />
# The TAP enable event also needs to be described<br />
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable<br />
jtag configure $_CHIPNAME.dap -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 3"<br />
<br />
# These taps are only present in the DM37x series.<br />
if { $CHIPTYPE == "dm37x" } {<br />
# Secondary TAP: Sequencer (ARM968) it is not in the chain by default<br />
# The ICEpick can be used to enable it in the chain.<br />
jtag newtap $_CHIPNAME arm2 -irlen 4 -ircapture 0x1 -irmask 0x0f -disable<br />
jtag configure $_CHIPNAME.arm2 -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 2"<br />
<br />
# Secondary TAP: C64x+ DSP - it is not in the chain by default (-disable)<br />
# The ICEpick can be used to enable it in the chain.<br />
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable<br />
jtag configure $_CHIPNAME.dsp -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 1"<br />
}<br />
<br />
# Secondary TAP: D2D it is not in the chain by default (-disable)<br />
# The ICEpick can be used to enable it in the chain.<br />
# This IRLEN is probably incorrect - not sure where the documentation is.<br />
jtag newtap $_CHIPNAME d2d -irlen 4 -ircapture 0x1 -irmask 0x0f -disable<br />
jtag configure $_CHIPNAME.d2d -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 0"<br />
<br />
# Primary TAP: ICEpick - it is closest to TDI so last in the chain<br />
eval "jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f $_JRC_TAPID"<br />
<br />
######<br />
# End of Chain Description<br />
######<br />
<br />
######<br />
# Start JTAG TAP events<br />
######<br />
<br />
# some TCK tycles are required to activate the DEBUG power domain<br />
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"<br />
<br />
# Enable the DAP TAP<br />
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"<br />
<br />
######<br />
# End JTAG TAP events<br />
######<br />
<br />
###############################################################################<br />
# Target Setup:<br />
# This section is described in the OpenOCD documentation under CPU Configuration<br />
# http://openocd.berlios.de/doc/html/CPU-Configuration.html<br />
###############################################################################<br />
<br />
# Create the CPU target to be used with GDB: Cortex-A8, using DAP<br />
set _TARGETNAME $_CHIPNAME.cpu<br />
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap<br />
<br />
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first<br />
# 16K to be used as a scratchpad for OpenOCD.<br />
<br />
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000<br />
<br />
######<br />
# Start Target Reset Event Setup:<br />
######<br />
<br />
# Set the JTAG clock down to 10 kHz to be sure that it will work with the<br />
# slowest possible core clock (16.8MHz/2 = 8.4MHz). It is OK to speed up<br />
# *after* PLL and clock tree setup.<br />
<br />
$_TARGETNAME configure -event "reset-start" { adapter_khz 10 }<br />
<br />
# Describe the reset assert process for openocd - this is asserted with the<br />
# ICEPick<br />
$_TARGETNAME configure -event "reset-assert" {<br />
<br />
global _CHIPNAME<br />
<br />
# assert warm system reset through ICEPick<br />
icepick_c_wreset $_CHIPNAME.jrc<br />
}<br />
<br />
# After the reset is asserted we need to re-initialize debugging and speed up<br />
# the JTAG clock.<br />
<br />
$_TARGETNAME configure -event reset-assert-post {<br />
<br />
global _TARGETNAME<br />
amdm37x_dbginit $_TARGETNAME<br />
adapter_khz 1000<br />
}<br />
<br />
$_TARGETNAME configure -event gdb-attach {<br />
<br />
global _TARGETNAME<br />
amdm37x_dbginit $_TARGETNAME<br />
<br />
echo "Halting target"<br />
halt<br />
}<br />
<br />
######<br />
# End Target Reset Event Setup:<br />
######<br />
<br />
###############################################################################<br />
# Target Functions<br />
# Add any functions needed for the target here<br />
###############################################################################<br />
<br />
# Run this to enable invasive debugging. This is run automatically in the<br />
# reset sequence.<br />
proc amdm37x_dbginit {target} {<br />
# General Cortex A8 debug initialisation<br />
cortex_a8 dbginit<br />
<br />
# Enable DBGEN signal. This signal is described in the ARM v7 TRM, but<br />
# access to the signal appears to be implementation specific. TI does not<br />
# describe this register much except a quick line that states DBGEM (sic) is<br />
# at this address and this bit.<br />
$target mww phys 0x5401d030 0x00002000<br />
}<br />
</syntaxhighlight><br />
<br />
[[Category:OpenOCD]]<br />
[[Category:Debugging]]</div>Wmat