http://elinux.org/index.php?title=Ar724x.cfg&feed=atom&action=history 2013-05-25T12:49:37Z Revision history for this page on the wiki MediaWiki 1.22alpha http://elinux.org/index.php?title=Ar724x.cfg&diff=135698&oldid=prev 2012-06-01T21:25:44Z

<p>Created page with &quot;&lt;syntaxhighlight code=&quot;tcl&quot;&gt; # Atheros AR724x MIPS 24Kc SoC. # tested on AP99 refererence board # # this settings are taken from source of u-boot for this board # (for PLL) file:...&quot;</p> <p><b>New page</b></p><div>&lt;syntaxhighlight code=&quot;tcl&quot;&gt;<br /> # Atheros AR724x MIPS 24Kc SoC.<br /> # tested on AP99 refererence board<br /> #<br /> # this settings are taken from source of u-boot for this board<br /> # (for PLL) file: u-boot/board/ar7240/common/lowlevel_init.S<br /> # (for DDR) file: u-boot/cpu/mips/ar7240/meminit.c<br /> # with file: u-boot/include/configs/ap99.h<br /> # to execute first part of initialization script <br /> # use this command: ar724x.cpu invoke-event reset-halt-post<br /> <br /> adapter_nsrst_delay 100<br /> jtag_ntrst_delay 100<br /> <br /> reset_config trst_only separate ;# or use only &quot;reset_config none&quot;<br /> #reset_config none<br /> <br /> set CHIPNAME ar724x<br /> <br /> jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1<br /> <br /> set TARGETNAME $CHIPNAME.cpu<br /> target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME<br /> <br /> <br /> $TARGETNAME configure -event reset-halt-post {<br /> #reset Watchdog Timer (when timer ends - resets SoC - then again halted)<br /> mww 0xb806000c 0x400000 ;# rst watchdog timer (delay ~250ms for JTAG adapter with slow speed)<br /> mww 0xb8060008 3 ;# rst watchdog timer control (set control bit in this delay window)<br /> <br /> sleep 250 ;# wait resetting SoC (delay for JTAG adapter with fast speed)<br /> poll ;# echo target state cpu (must be: running)<br /> halt<br /> <br /> #setup PLL to lowest(default) common denominator 400/400/200 setting<br /> mww 0xb8050000 0x00090828 ;# clr pll mask (rst:02090828)<br /> mww 0xb8050000 0x00050828 ;# CPU:400 DDR:400 AHB:200<br /> mww 0xb8050000 0x00040828 ;# clr pll bypass<br /> <br /> #next command will reset for PLL changes to take effect <br /> mww 0xb8050008 2 ;# set reset_switch<br /> mww 0xb8050008 3 ;# set clock_switch (resets SoC)<br /> }<br /> <br /> $TARGETNAME configure -event reset-init {<br /> #complete pll initialization<br /> mww 0xb8050008 0 ;# set reset_switch bit &amp; clock_switch bit<br /> <br /> # Setup DDR config and flash mapping<br /> mww 0xb8000000 0xc7bc8cd0 ;# DDR cfg cdl val (rst:77be8cd0)<br /> mww 0xb8000004 0x9dd0e6a8 ;# DDR cfg2 cdl val (rst:99d10628)<br /> <br /> mww 0xb8000010 8 ;# force precharge all banks<br /> mww 0xb8000008 0x133 ;# DDR mode value init<br /> mww 0xb8000010 1 ;# force EMRS update cycle<br /> mww 0xb800000c 0 ;# clr ext. mode register<br /> <br /> mww 0xb8000010 2 ;# force auto refresh all banks<br /> mww 0xb8000010 8 ;# force precharge all banks<br /> mww 0xb8000008 0x33 ;# set DDR mode value CAS=3<br /> mww 0xb8000010 1 ;# force EMRS update cycle<br /> mww 0xb8000014 0x4f10 ;# DDR refresh value<br /> mww 0xb8000018 0xff ;# DDR Read Data This Cycle value (16bit: 0xffff)<br /> mww 0xb800001c 2 ;# delay added to the DQS0 line (normal = 7)<br /> mww 0xb8000020 2 ;# delay added to the DQS1 line (normal = 7)<br /> mww 0xb8000024 0<br /> mww 0xb8000028 0<br /> }<br /> <br /> # setup working area somewhere in RAM<br /> $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000<br /> <br /> # serial SPI capable flash<br /> # flash bank &lt;driver&gt; &lt;base&gt; &lt;size&gt; &lt;chip_width&gt; &lt;bus_width&gt;<br /> &lt;/syntaxhighlight&gt;<br /> <br /> =Source=<br /> http://wiki.openwrt.org/ru/toh/tp-link/tl-mr3420/debrick.using.jtag<br /> <br /> [[Category:OpenOCD]]<br /> [[Category:Debugging]]</div>

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