Difference between revisions of "BCM2835 datasheet errata"

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(p158)
(p153)
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top line: device should be devise.
 
top line: device should be devise.
 
== p153 ==
 
== p153 ==
Typo: wrirng -> writing.
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Typo: wrirng -> writing.
 
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Consider CSPOLx -> CPOLx (see p158 below).  
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== p158 ==  
 
== p158 ==  

Revision as of 08:04, 18 April 2012

Back to RPi_Hardware#Components


BCM 2835 datasheet errata

The (partial) datasheet was published here: at raspberrypi.org and a mirror

It has a couple of typos. Some more serious than others.

Let's gather those datasheet typos and errors here.

The quality of the datasheet is high. It looks like it contains the information that programmers need.

It also "does the right thing" with reserved bits. Many datasheets specify "write: don't care, read as zeroes". Broadcom specifies the reserved bits the other way around: "Write zeroes, read: don't care".

This is the correct way to do it. If you expand the hardware the hardware may be enhanced and do "different things" if you write ones to the previously "reserved" bits. If you follow the datasheet, and write zeroes as specified to the reserved bits, the hardware guys can make sure you're not going to run into surprises. And by specifying "read: don't care" you can allow future hardware to provide status bits there.

PDF Generation

Switch on option for linking, so cross-references and table of contents can be jumped through.

p7 footnote typo

precuations should be precautions.

p8

The register names are AUX_SPI0_.... and AUX_SPI1_.... . The "description" is then SPI 1 ... and SPI 2 ....

These modules are in fact SPI1 and SPI2, and NOT SPI0 and SPI1. This is confusing as indeed there is a different module called SPI0 (documented on page 148 and onwards).

p25 table

"AUX is IDLE:" should read "SPI is idle". (and for consistency below the line "Interrupts", SPI is Idle should be spelled "SPI is idle".

The table on page 25 has the bit numbers wrong. Some bits are mentioned twice, some not at all.

I'm guessing it should be something like:

Bit(s) Field Name Description type reset
31:24 TX FIFO level The number of data units in the transmit data FIFO R/W 0
23:16 RX FIFO level The number of data units in the receive data FIFO. R/W 0
15:10 - Reserved, write zero, read as don’t care R/W 0
9 TX Full If 1 the transmit FIFO is full
If 0 the transmit FIFO can accept at least 1 data unit.
R/W 0
8 TX Empty If 1 the transmit FIFO is empty R/W 0
If 0 the transmit FIFO holds at least 1 data unit.
R/W 0
7 RX Empty If 1 the receiver FIFO is empty R/W 0
If 0 the receiver FIFO holds at least 1 data unit.
R/W 0
6 Busy Indicates the module is busy transferring data. R/W 0
5:0 Bit count The number of bits still to be processed. Starts with 'shift-length' and counts down. R/W 0


The register reads as 0x280 after reset. Two bits high would be consistent with TX empty and RX empty. However, bits 7 and 9 does not match the original datasheet, nor my guess.....

p26

The Peek register is documented here as being at 0x7e21508c, whereas the table on page 8 shows 0x7e215094.

The IO register is documented as 0x7e2150a0 (with automatic deassert) and 0x7e2150b0, whereas the table on page 8 shows 0x7e215090.

p34 off-by-one?

I strongly suspect that the CDIV counter is only 14 bits wide. The bottom bit doesn't work as per specifications, and because the "0" results in 32768, the top bit doesn't either. An easy implementation would implement the 0 value as the maximum divisor. Not as "half the maximum".

Another option is that SCL = cor clock * 2 / CDIV and that the counter is 15 bits after all. (only the lowest bit missing).


p38 typo

harware instead of hardware (second paragraph)

p90

address 0x7e20 0000 is listed twice as gpfsel0.

p95

There is a spurious ) in "..clear registers) are used..."

p104 table

The table, legend for table 6-31, started on page 103 shows in red: TXD0, RXD0, CTS0, RTS0 which should be TXD1, RXD1, CTS1, RTS1.

p111 spelling

top line: device should be devise.

p153

Typo: wrirng -> writing.

p158

Multiple references are made to CPOL bits. These are documented in the register bit descriptions (p153) as CSPOL.

p160

The registers base addresses -> the registers' base address or The base address of the registers is 0x7e21_4000.

p175

top line. Two typos:

On mini UART and and PL011 UART

should be

One mini UART and one PL011 UART

p177

13.4 register view

The base address is listed as 0x7e20100 . This should be 0x7e201000.

p202

The last entry of section 15.1.

The entries in the table should specify the choice that Broadcom made when instantiating the USB controller IP from Synopsys.

Possibly the "choice" hasn't been specified. Or maybe the "0=32, 1..5=512, 6,7=768" is the option that was chosen?