BSDL

From eLinux.org
Revision as of 03:35, 1 March 2007 by Wmat (Talk | contribs)

(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

Boundary Scan Description Language (BSDL) is a subset of VHDL that is used to describe how JTAG (IEEE 1149.1) is implemented in a particular device. For a device to be JTAG compliant, it must have an associated BSDL file. These files are often available for download from manufacturers' websites.

JTAG systems use the information contained in a BSDL file to work out how to access a device in the JTAG chain.

BSDL files contain the following elements:

  • Entity Description: Statements naming the device or a section of its functionality.
  • Generic Parameter: A value such as a package type. The value may come from outside the current entity.
  • Port Description: Describes the nature of the pins on the device (input, output, bidirectional, linkage).
  • Use Statements: References external definitions (such as IEEE 1149.1).
  • Pin Mapping(s): Maps logical signals in the device to physical pins.
  • Scan Port Identification: Defines the pins used on the device to access the JTAG capabilities (TDI, TDO, etc - the Test Access Port).
  • Instruction Register Description: The signals used for accessing JTAG device modes.
  • Register Access Description: Which register is placed between TDI and TDO for each JTAG instruction.
  • Boundary Register Description: List of the boundary scan cells and their functionality.