There are three pins capable of PWM (pulse-width modulation) exposed on the C3/C4 BeagleBoard expansion header. PWM is useful for control of a number of devices, from LEDs (which can be faded smoothly with PWM) to DC motors. For robotics, this means that three hobby servos can easily be controlled by the Beagle given nothing more than a simple level-shifting circuit.
OMAP Mux Configuration
Because the PWM pins are not set as such by default, the OMAP's mux must be configured to expose them before they can be used. See BeagleBoardPinMux for more details on this procedure. The short version is to add the following lines to the definition of
board_mux in arch/arm/mach-omap2/board-omap3beagle.c (this has been tested with the 2.5.32 OMAP branch of the kernel).
OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE2|OMAP_PIN_OUTPUT), /* GPT9_PWMEVT, ball AB26, ex pin 4 */ OMAP3_MUX(UART2_TX, OMAP_MUX_MODE2|OMAP_PIN_OUTPUT), /* GPT11_PWMEVT, ball AA25, ex pin 6 */ OMAP3_MUX(UART2_RTS, OMAP_MUX_MODE2|OMAP_PIN_OUTPUT), /* GTP10_PWMEVT, ball AB25, ex pin 10 */
Obviously these lines should precede the line terminating the array.
Activating PWM via Timer Registers
PWM output on the BeagleBoard is done via the OMAP processor's general-purpose timer mechanism, described in the OMAP35x TRM in section 16.2.4 (page 2546). To briefly summarize this (and simplify significantly), the general-purpose timer is a continuously-incrementing counter that can be configured to toggle the PWM output high when a certain value is reached, and low when it overflows. By adjusting the first number the duty cycle can be set. Setting the value the counter starts at can be used to set the frequency of the PWM.
Each GP timer has a 4K block for memory-mapped registers (see TRM Table 16-12). The start addresses of these blocks for the timers on the BeagleBoard are listed below.
|Timer||Base address||Expansion header pin|
These are the registers relevant to our purpose:
|TCLR||126.96.36.199 (p. 2568)||0x024||Control register.|
|TCRR||188.8.131.52 (p. 2570)||0x028||The counter. Increments with the clock when the timer is running.|
|TLDR||184.108.40.206 (p. 2571)||0x02c||Timer load register. Holds the value assumed by TCRR when it overflows.|
|TMAR||220.127.116.11 (p. 2575)||0x038||Value to be compared with the counter.|