BeagleBone 6502 RemoteProc cape

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BeagleBone 6502 RemoteProc cape

The BeagleBone 6502 RemoteProc cape is a prototype project that interfaces a WDC65C02S microprocessor to the BeagleBone host. The AM335x SoC on the BeagleBone emulates 65xx bus cycles utilizing the Ti_AM33XX_PRUSSv2.

Hardware Design

The following diagram shows a high-level schematic of the b6502 cape. The number of PRU pins available are limited so bus cycles are sampled by the PRU asserting a series of octal bus transceiver enables. In a read cycle, address high, address low, and data out are enabled in sequence. For a write cycle, address high, address low, and data in are enabled in sequence. This allows the PRU to wait for a clock edge, sample the R/W signal, and then fetch the address and data for the read or write operation. To complete the cycle, the PRU reads or writes to its local SRAM, providing the data to the 6502 on a read cycle or storing the data on a write cycle.

BeagleBone 6502 Schematic

A Fritzing diagram illustrates the wiring of the prototype on a breadboard.

BeagleBone 6502 Fritzing