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Difference between revisions of "BeagleBone PRU Notes"

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[[Category:ECE497Notes |PRU]]
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The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).
 
The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).
  
== BeagleBone PRU ==
+
== BeagleBone Programmable Real-time Unit ==
 
This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.
 
This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.
  
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There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.
 
There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.
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Data Sheet is located at http://www.ti.com/lit/pdf/spruh73
  
 
=== Software examples ===
 
=== Software examples ===
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These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.
 
These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.
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 +
Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide
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=== Instruction Set ===
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Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)
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==== Four instruction classes ====
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* Arithmetic
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* Logical
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* Flow Control
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* Register Load/Store
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==== Instruction Syntax ====
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* Mnemonic, followed by comma separated parameter list
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* Parameters can be a register, label, immediate value, or constant table entry
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* Example
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** SUB r3, r3, 10
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** Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3
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==== Example Assembly ====
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<pre>
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;INTC_SIR_IRQ/INTC_SIR_FIQ register address
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INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044
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; ACTIVEIRQ bit field mask to get only the bit field
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ACTIVEIRQ_MASK .equ 0x7F
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_IRQ_ISR/_FIQ_ISR:
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; Save the critical context
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STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register
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MRS R11, SPSR ; Save the SPSR into R11
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; Get the number of the highest priority active IRQ/FIQ
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LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR
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LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register
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AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number
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; Jump to relevant subroutine handler
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LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8
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NOP ; To index the table by the PC
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; Table of handler start addresses
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.word IRQ0handler ;For IRQ0 of BANK0
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.word IRQ1handler
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.word IRQ2handler
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</pre>
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== Leads ==
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Here's some sources of information. 
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 +
* [http://www.element14.com/community/community/knode/single-board_computers/next-gen_beaglebone/blog/2013/05/22/bbb--working-with-the-pru-icssprussv2 BBB - Working with the PRU-ICSS/PRUSSv2]  Has very detailed instructions for working with the Black.
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* [http://git.mah.priv.at/gitweb?p=emc2-dev.git;a=shortlog;h=refs/heads/arm335x-hal-pru-tasks Working PRU examples]

Revision as of 15:23, 5 June 2013


The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).

BeagleBone Programmable Real-time Unit

This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.

Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.

PRU capabilities

AM335x PRUSS

  • The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).
  • 8KB data memory and 8KB instruction memory
  • 12KB shared RAM
  • A small, deterministic instruction set

There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.

Data Sheet is located at http://www.ti.com/lit/pdf/spruh73

Software examples

BeagleBoard/TI has provided example C programs that utilize the PRU on github.

These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.

Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide

Instruction Set

Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)

Four instruction classes

  • Arithmetic
  • Logical
  • Flow Control
  • Register Load/Store

Instruction Syntax

  • Mnemonic, followed by comma separated parameter list
  • Parameters can be a register, label, immediate value, or constant table entry
  • Example
    • SUB r3, r3, 10
    • Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3

Example Assembly

;INTC_SIR_IRQ/INTC_SIR_FIQ register address
INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044
; ACTIVEIRQ bit field mask to get only the bit field
ACTIVEIRQ_MASK .equ 0x7F
_IRQ_ISR/_FIQ_ISR:
; Save the critical context
STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register
MRS R11, SPSR ; Save the SPSR into R11
; Get the number of the highest priority active IRQ/FIQ
LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR
LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register
AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number
; Jump to relevant subroutine handler
LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8
NOP ; To index the table by the PC
; Table of handler start addresses
.word IRQ0handler ;For IRQ0 of BANK0
.word IRQ1handler
.word IRQ2handler

Leads

Here's some sources of information.