Difference between revisions of "ECE597 Project Network based OGG player"
Revision as of 05:30, 18 May 2010
This project is part of the ECE597 32-bit Embedded Linux class at Rose-Hulman Institute of Technology in Terre Haute, IN.
The goal of this project is to have the Beagleboard act as a network based mp3 player. The Beagle will be programmed using a custom, protocol for transferring files from a network based server (x86 pc) to a Beagle. Speakers will be attached to the Beagle, where the file will be played back. Possible extensions are a LCD for displaying id3 tag information, and buttons for user interaction (next track, previous track, etc.) on the GPIO interface.
1 - C4 BeagleBoard
1 - .1” (100 thou) header
1 - LCD Display: NHD-C0216Ciz-FS-FBW-3V3
1 - Logic Level Shifter: BOB-08745
1 - 3.3 V Voltage Regulator: LT1086 CT
2 – 10uF Capacitors
3 – 1uF Capacitors
1 – 1kΩ Resistor
C4 Beagle Expansion
In order to use the expansion header on the BeagleBoard, a .100 header was soldered onto J3. The useful pins for this project are noted below.
Pin 1 – 1.8V
Pin 2 – 5V
Pin 23 - SDA
Pin 24 - SCL
Pin 27 – GND
Making I2C2 work on the BeagleBoard can be a bit tricky. Take a look at Interfacing_with_I2C_Devices#Beagleboard_I2C2_Enable for some tips.
Pin 1 – RST
Pin 2 – SCL
Pin 3 – SDA
Pin 4 – Vss
Pin 5 – Vdd
Pin 6 – Vout
Pin 7 – C1+
Pin 8 – C1-
The 2 capacitors should have a value of 1 uF. The 2 pull-up resistors will not be necessary due to the pull-up resistors in the logic level shifters (see below). The slave address of the I2C interface protocol is 0x7c. Pin 1 will be tied high, pins 2 and 3 are the SCL, SDA pins respectively, and will therefore go through the logic level shifter below. Pin 4 will be tied to ground. Pin 5 will be tied to the 3.3V. Pin 6 will have a 1 uF capacitor tied to pin 5. Pin 7 will have a 1 uF capacitor tied to pin 8. Consult the datasheet for further information.
Logic Level Shifter
The 1.8V supplied from the Beagle we be connected to the LV pin. The HV side will be powered with 3.3v from the voltage regulator
3.3V Voltage Regulator
Initially the level shifter and lcd display were tested using an arduino as we already had working I2C code for the AVR. Once the LCD initilization pattern and was functioning correctly the circuit was then rewired to accommodate the 1.8V of the BeagleBoard.
In the ECE597 lab kit, we were provided a USB->5V adapter for powering the beagle. However there appears to be an issue with newer kernels drawing too much power to actually run the beagle off of USB. The 5V pin on J3 was only outputting 3.9V. In order properly power the Beagle, a wall-wart needs to be used; which caused the 5V pin on J3 to be a steady 5.1v.
Additionally a 1uF capacitor was tied to the 1.8V supplied by the BeagleBoard expansion pin 1 to ensure that in peak power demand, the pin level shifter would have a more reliable power supply. With everything in place the code and circuit were tested. However it was observed that there was not consistent data transmission between the beagle and the LCD. The I2C bus would sometimes report Remote I/O errors. The the i2c level shifter was tested at the new voltage on an oscilloscope and using a 1.8v 400khz (same frequency as the i2c bus) square wave created by a function generator. The behavior was not quite as would be expected. There bus was not reliably reaching 3.3V on the output of the level shifter, and the waves were not square. The output looked more like a charging capacitor. As speed is not a issue in our system, our solution was to reduce the clock frequency of the i2c bus from 400khz to 50khz. This adjustment produced reliable results, which allowed the correct and reliable communication with the LCD.