ECE597 Project Network based OGG player
This project is part of the ECE597 32-bit Embedded Linux class at Rose-Hulman Institute of Technology in Terre Haute, IN.
The goal of this project is to have the Beagleboard act as a network based mp3 player. The Beagle will be programmed using a custom, protocol for transferring files from a network based server (x86 pc) to a Beagle. Speakers will be attached to the Beagle, where the file will be played back. Possible extensions are a LCD for displaying id3 tag information, and buttons for user interaction (next track, previous track, etc.) on the GPIO interface.
1 - C4 BeagleBoard
1 - .1” (100 thou) header
1 - LCD Display: NHD-C0216Ciz-FS-FBW-3V3
1 - Logic Level Shifter: BOB-08745
1 - 3.3 V Voltage Regulator: LT1086 CT
2 – 10uF Capacitors
3 – 1uF Capacitors
1 – 1kΩ Resistor
(Optional Voltage Dividers)
2 – 2kΩ Resistors
2 – 1.2kΩ Resistors
C4 Beagle Expansion
In order to use the expansion of the C4 BeagleBoard, a .1” (one hundred thou) header, either male or female, needs to be soldered to the board. For this project the following pins will be used.
Pin 1 – 1.8V
Pin 2 – 5V
Pin 23 - SDA
Pin 24 - SCL
Pin 27 – GND
Making I2C2 work on the C4 BeagleBoard can be a bit tricky. First in order to make the I2C2 work on the BeagleBoard, the patch found here, must be applied. Additional help can be found here. The necessary changes to the U-Boot and Kernel can be found here and here. The latest can be found here. Additional notes on I2C2, such as not enabling I2C2 unless something is actually connected, can be found here.
Pin 1 – RST
Pin 2 – SCL
Pin 3 – SDA
Pin 4 – Vss
Pin 5 – Vdd
Pin 6 – Vout
Pin 7 – C1+
Pin 8 – C1-
The 2 capacitors should have a value of 1 uF. The 2 pull-up resistors will not be necessary due to the pull-up resistors in the logic level shifters (see below). The slave address of the I2C interface protocol is 0x7c. Pin 1 will be tied high, pins 2 and 3 are the SCL, SDA pins respectively, and will therefore go through the logic level shifter below. Pin 4 will be tied to ground. Pin 5 will be tied to the 3V signal of the voltage divider. Pin 6 will have a 1 uF capacitor tied to pin 5. Pin 7 will have a 1 uF capacitor tied to pin 8. Pin A will be tied to the 3V signal from the voltage divider. Pin k will be tied to ground.
Logic Level Shifter
The 1.8V supplied from the Beagle we be connected to the LV pin. The 5V supplied via pin 2 on the beagle will supply the HV pin after the voltage regulator to produce 3.3V.
3.3V Voltage Regulator
Optional Voltage Divider
For our purposes R1 will be set to 1.2k and R2 to 2k to ensure a 5V to 3V signal.
Initially the level shifter and lcd display were tested on an arduino. During testing it was determined that the use of 2 voltage dividers would be beneficial, one for the i2c communication and one for the reset and backlight of the lcd. With this adjustment everything proved to be working. The circuit was then rewired to accommodate the 1.8V of the BeagleBoard.
When powering the BeagleBoard via USB there is an unreliable amount of power that can partially be stabilized via the serial cable, however greatly fluctuates as serial communication occurs; however, regardless the power was never greater that 3.9V. In order properly power the Beagle, a wall outlet needs to be used. While using the wall outlet stabilized the 5V supply of the BeagleBoard expansion pin 2, it did not stabilize the 3V supplied by the voltage divider during i2c communication; therefore a LT1086 CT 3.3 V regulator was used in conjunction with 2 10uF capacitors as specified by the datasheet.
Additionally a 1uF capacitor was tied to the 1.8V supplied by the BeagleBoard expansion pin 1. With everything in place the code and circuit were tested. However it was observed that there was not a consistent read of data across the LCD, and additionally there would be Remote I/O errors on the Beagle. Therefore the i2c busses across the logic level shifter were observed, and the behavior was not quite as would be expected, as there was some data not always reaching high and low. Additionally the clock was not perfectly square. Therefore, for debugging purposes, a 1.8V square wave operating at the same 400 kHz as the BeagleBoard was attached to the SCL line and the input and output were observed via the oscilloscope. This revealed that the logic level shifters were taking a 1.8V square wave input and producing a non square output. However, by reducing the frequency the output could be made to appear squarer. Therefore the BeagleBoard kernel was adjusted such that the Beagle would operate at 50 kHz as opposed to the standard 400 kHz. This adjustment produced reliable results, which allowed the message to be adjusted and viewed via the LCD.