Difference between revisions of "Embedded Open Modular Architecture/CompactFlash"

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= EOMA/CF =
 
= EOMA/CF =
  
page under development.  this standard is virtually identical to EOMA-68 except that the 24-pin RGB/TTL has been replaced by single-channel LVDS.
+
page under development.
  
the disadvantage of single-channel LVDS is that it is not sufficient to drive resolutions above 1280x1024 @ 75hz (24-bit) but if a lower refresh rate (40hz, 30hz) is acceptable, and/or a lower bitrate (18-bit) then it is possible to drive 1920x1080 at about 60hz for 18-bit or 47hz for 24-bit.
+
this standard is primarily designed for ultra-low-cost systems as well as those where space is at a premium.  because of this, specifying MIPI as the LCD standard would be inappropriate, as indeed would eDP.  even in cases where the SoC does not have LVDS, a low-cost RGB/TTL to LVDS IC is available such as the [TI SN75LVDS83b](http://www.ti.com/product/sn75lvds83).  so for the low end market, connection to 320x240 (or even smaller) LCDs is directly possible via RGB/TTL, and for the high-end market conversion via LVDS or MIPI ICs is possible on the other side of the interface (e.g. via the [SSD2828](http://www.solomon-systech.com/en/product/display-ic/mipi-master-bridge-chip/ssd2828/).
 
+
this standard is primarily designed for ultra-low-cost systems as well as those where space is at a premium.  because of this, specifying MIPI as the LCD standard would be inappropriate, whereas many SoCs now have single-channel or in some case dual-channel LVDS available as standard.  even in cases where the SoC does not have LVDS, a low-cost RGB/TTL to LVDS IC is available such as the [TI SN75LVDS83b](http://www.ti.com/product/sn75lvds83).
+
  
 
the edge of the CF card can have as many connectors as will fit into a 43mm width.  Micro-HDMI Type D, USB-OTG and a 2.5mm 4-pin Headphone Jack can be considered.  A MicroSD slot could be placed on one of the side edges (requiring the module to be removed and switched off in order to access it, as is the case with most mobile phones).
 
the edge of the CF card can have as many connectors as will fit into a 43mm width.  Micro-HDMI Type D, USB-OTG and a 2.5mm 4-pin Headphone Jack can be considered.  A MicroSD slot could be placed on one of the side edges (requiring the module to be removed and switched off in order to access it, as is the case with most mobile phones).
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TODO: ensure no clash with power pins http://pinouts.ru/Memory/CompactFlash_pinout.shtml
 
TODO: ensure no clash with power pins http://pinouts.ru/Memory/CompactFlash_pinout.shtml
  
These pinouts make no attempt to be electrically or electronically compatible with the existing CompactFlash standard. 16 GPIO pins, Single-channel LVDS for LCD, USB2, I2C, 10/100/1000 Ethernet and SATA-II interfaces are included in the Version 1.0 specification. Note: USB2, SATA-II and Ethernet ''must'' support auto-negotiation, and must support the lower capabilities (USB 1, USB 1.1, SATA-I, 10/100 Ethernet). Higher speeds and capabilities are optional.
+
These pinouts make no attempt to be electrically or electronically compatible with the existing CompactFlash standard. 16 GPIO pins, 15-pin RGB/TTL for LCD, USB2, USB3, I2C, SD/MMC, SPI and UART interfaces are included in the Version 1.0 specification. Note: USB2 and USB3 ''must'' support auto-negotiation, and must support the lower capabilities (USB 1, USB 1.1, USB 2, USB 3.0, USB 3.1). Higher speeds and capabilities are optional.
  
 
Two 5.0v power inputs must be provided: all pins are rated at 0.5 amps, so the maximum power dissipation is limited to 5 watts. Design consideration: please note that to ensure that thermal dissipation in an enclosed fanless situation is not exceeded, a maximum of 3.5 watts should be respected. Most systems will not have active cooling.
 
Two 5.0v power inputs must be provided: all pins are rated at 0.5 amps, so the maximum power dissipation is limited to 5 watts. Design consideration: please note that to ensure that thermal dissipation in an enclosed fanless situation is not exceeded, a maximum of 3.5 watts should be respected. Most systems will not have active cooling.
  
All High-speed signals (LVDS, USB2, Ethernet, SATA-II) are balanced lines that are still separated using GND or Power pins. All other pins are low frequency.  The sixteen GPIO pins are available, for general-purpose bi-directional use of digital data only.
+
All High-speed signals (USB2, USB3) are balanced lines that are still separated using GND or Power pins. All other pins are low frequency.  
  
The typical voltages of the LVDS LCD lines should be compatible with the LVDS output from a Texas Instruments SN75LVDS83b, i.e. 1.25V +/- 0.125V, and the peak-to-peak common-mode output voltage around 150mV, as illustrated in Figure 3 of the SN75LVDS83b datasheet.
+
The typical voltages of the RGB/TTL LCD lines should be compatible with a Texas Instruments SN75LVDS83b, i.e. 1.25V +/- 0.125V, 5V tolerant, and the peak-to-peak common-mode output voltage around 150mV, as illustrated in Figure 3 of the SN75LVDS83b datasheet.
  
 
Also, because the GPIO pins can be reconfigured individually bi-directional for any digital purposes, they *must* be made to be 5V TTL tolerant and tri-state isolated, and Motherboards also must be 5.0v TTL tolerant as well as tri-state isolated. Levels when any GPIO pin is used either as an input or as an output should again operate at nominal 3.3v TTL levels, thus expect "High" Voltage of 2.0 volts, threshold of 1.4v and "Low" voltage of 0.8v.
 
Also, because the GPIO pins can be reconfigured individually bi-directional for any digital purposes, they *must* be made to be 5V TTL tolerant and tri-state isolated, and Motherboards also must be 5.0v TTL tolerant as well as tri-state isolated. Levels when any GPIO pin is used either as an input or as an output should again operate at nominal 3.3v TTL levels, thus expect "High" Voltage of 2.0 volts, threshold of 1.4v and "Low" voltage of 0.8v.
  
The option to use Gigabit Ethernet is also available, if a given system has it. If, however, a particular system does not have Gigabit Ethernet, the pins must not be used for other purposes, and must be left unconnected. This is to ensure that automatic negotiation of 100/1000 Ethernet occurs correctly.  
+
The maximum LCD Resolution supported must be at least 1440x900 @ 60fps, however there is no restriction on reducing the number of bits per pixel (to 8bpp or even to monochrome) if a particular low-cost SoC has severe video bandwidth limitations in achieving that resolution.
  
 
=== Table of EOMA-CF pinouts ===
 
=== Table of EOMA-CF pinouts ===
Line 30: Line 28:
 
!style="width:50%"|Row 2
 
!style="width:50%"|Row 2
 
|-
 
|-
|* 1    RIN 0-      Negative LVDS differential data output
+
|* 1    LCD Pixel Data bit 3 (Red3)
|* 26    RIN 0+  Positive LVDS differential data output
+
|* 26    LCD Pixel Data bit 4 (Red4)
 
|-
 
|-
|* 2    RIN 1-  Negative LVDS differential data output
+
|* 2    LCD Pixel Data bit 5 (Red5)
|* 27    RIN 1+  Positive LVDS differential data output
+
|* 27    LCD Pixel Data bit 6 (Red6)
 
|-
 
|-
|* 3    RIN 2-  Negative LVDS differential data output
+
|* 3    LCD Pixel Data bit 7 (Red7)
|* 28    RIN 2+  Positive LVDS differential data output
+
|* 28    LCD Pixel Data bit 11 (Green3)
 
|-
 
|-
|* 4    CLKIN-  Negative LVDS differential clock output
+
|* 4    LCD Pixel Data bit 12 (Green4)
|* 29    CLKIN+  Positive LVDS differential clock output
+
|* 29    LCD Pixel Data bit 13 (Green5)
 
|-
 
|-
|* 5 GROUND
+
|* 5     LCD Pixel Data bit 14 (Green6)
|* 30 GROUND
+
|* 30   LCD Pixel Data bit 15 (Green7)
 
|-
 
|-
|* 6 ---- not used ---- / 1000 Eth BI_DD+
+
|* 6     LCD Pixel Data bit 19 (Blue3)
|* 31 ---- not used ---- / 1000 Eth BI_DD-
+
|* 31   LCD Pixel Data bit 20 (Blue4)
 
|-
 
|-
|* 7 10/100 Ethernet (RX+) / 1000 Eth BI_DB+
+
|* 7     LCD Pixel Data bit 21 (Blue5)  
|* 32 10/100 Ethernet (RX-) / 1000 Eth BI_DB-
+
|* 32     LCD Pixel Data bit 22 (Blue6)  
 
|-
 
|-
|* 8 10/100 Ethernet (TX+) / 1000 Eth BI_DA+
+
|* 8     LCD Pixel Data bit 23 (Blue7)  
|* 33 10/100 Ethernet (TX-) / 1000 Eth BI_DA-
+
|* 33   LCD Pixel Clock
 
|-
 
|-
|* 9 ---- not used ---- / 1000 Eth BI_DC+
+
|* 9 GROUND
|* 34 ---- not used ---- / 1000 Eth BI_DC-
+
|* 34 GROUND
 
|-
 
|-
|* 10 GROUND
+
|* 10 GPIO (0) / SDMMC-D3
|* 35 GROUND
+
|* 35 GPIO (1) / SDMMC-D2
 
|-
 
|-
|* 11 USB2 (Data-)
+
|* 11 GPIO (2) / UART-TX
|* 36 USB2 (Data+)
+
|* 36 GPIO (3) / UART-RX
 
|-
 
|-
|* 12 PWR (5.0V)
+
|* 12 GPIO (4) / SDMMC-CMD
|* 37 PWR (5.0v)
+
|* 37 GPIO (5) / SDMMC-CLK
 
|-
 
|-
|* 13 GPIO (0)
+
|* 13 GPIO (6) / SDMMC-D0
|* 38 GPIO (1)
+
|* 38 GPIO (7) / SDMMC-D1
 
|-
 
|-
|* 14 GPIO (2)
+
|* 14 I2C Clock (SCL)
|* 39 GPIO (3)
+
|* 39 I2C Data (SDA)
 
|-
 
|-
|* 15 GPIO (4)
+
|* 15 GPIO (10) / PWM
|* 40 GPIO (5)
+
|* 40 LCD Vertical Synchronization
 
|-
 
|-
|* 16 GPIO (6)
+
|* 16 LCD Horizontal Synchronization
|* 41 GPIO (7)
+
|* 41 LCD Pixel data enable (TFT) output
 
|-
 
|-
|* 17 GPIO (8)
+
|* 17 GPIO (12) / SPI_MISO
|* 42 GPIO (9)
+
|* 42 GPIO (13) / SPI_MOSI
 
|-  
 
|-  
|* 18 GPIO (10)
+
|* 18 GPIO (14) / SPI_SCK
|* 43 GPIO (11)
+
|* 43 GPIO (15) / EINT1
 
|-
 
|-
|* 19 GPIO (12)
+
|* 19 ---- not used ---- / USB3 StdA_SSRX-
|* 44 GPIO (13)
+
|* 44 ---- not used ---- / USB3 StdA_SSRX+
 
|-
 
|-
|* 20 GPIO (14)
+
|* 20 ---- not used ---- / USB3 StdA_SSTX-
|* 45 GPIO (15)
+
|* 45 ---- not used ---- / USB3 StdA_SSTX+
 
|-
 
|-
|* 21 I2C Clock (SCL)
+
|* 21 USB2 (Data-)
|* 46 I2C Data (SDA)
+
|* 46 USB2 (Data+)
 
|-
 
|-
|* 22 GROUND
+
|* 22 PWR (5.0V)
|* 47 GROUND
+
|* 47 PWR (5.0v)
 
|-
 
|-
|* 23 SATA-II Transmit (A+)
+
|* 23 GPIO (11) / EINT0
|* 48 SATA-II Transmit (A-)
+
|* 48 VREF-TTL (GPIO TTL Voltage Reference)
 
|-
 
|-
 
|* 24 GROUND
 
|* 24 GROUND
 
|* 49 GROUND
 
|* 49 GROUND
 
|-
 
|-
|* 25 SATA-II Receive (B+)
+
|* 25 2nd USB2 (Data+)
|* 50 SATA-II Receive (B-)
+
|* 50 2nd USB2 (Data-)
 
|}
 
|}
  

Latest revision as of 00:45, 14 January 2015

EOMA/CF

page under development.

this standard is primarily designed for ultra-low-cost systems as well as those where space is at a premium. because of this, specifying MIPI as the LCD standard would be inappropriate, as indeed would eDP. even in cases where the SoC does not have LVDS, a low-cost RGB/TTL to LVDS IC is available such as the [TI SN75LVDS83b](http://www.ti.com/product/sn75lvds83). so for the low end market, connection to 320x240 (or even smaller) LCDs is directly possible via RGB/TTL, and for the high-end market conversion via LVDS or MIPI ICs is possible on the other side of the interface (e.g. via the [SSD2828](http://www.solomon-systech.com/en/product/display-ic/mipi-master-bridge-chip/ssd2828/).

the edge of the CF card can have as many connectors as will fit into a 43mm width. Micro-HDMI Type D, USB-OTG and a 2.5mm 4-pin Headphone Jack can be considered. A MicroSD slot could be placed on one of the side edges (requiring the module to be removed and switched off in order to access it, as is the case with most mobile phones).

Pinouts

TODO: ensure no clash with power pins http://pinouts.ru/Memory/CompactFlash_pinout.shtml

These pinouts make no attempt to be electrically or electronically compatible with the existing CompactFlash standard. 16 GPIO pins, 15-pin RGB/TTL for LCD, USB2, USB3, I2C, SD/MMC, SPI and UART interfaces are included in the Version 1.0 specification. Note: USB2 and USB3 must support auto-negotiation, and must support the lower capabilities (USB 1, USB 1.1, USB 2, USB 3.0, USB 3.1). Higher speeds and capabilities are optional.

Two 5.0v power inputs must be provided: all pins are rated at 0.5 amps, so the maximum power dissipation is limited to 5 watts. Design consideration: please note that to ensure that thermal dissipation in an enclosed fanless situation is not exceeded, a maximum of 3.5 watts should be respected. Most systems will not have active cooling.

All High-speed signals (USB2, USB3) are balanced lines that are still separated using GND or Power pins. All other pins are low frequency.

The typical voltages of the RGB/TTL LCD lines should be compatible with a Texas Instruments SN75LVDS83b, i.e. 1.25V +/- 0.125V, 5V tolerant, and the peak-to-peak common-mode output voltage around 150mV, as illustrated in Figure 3 of the SN75LVDS83b datasheet.

Also, because the GPIO pins can be reconfigured individually bi-directional for any digital purposes, they *must* be made to be 5V TTL tolerant and tri-state isolated, and Motherboards also must be 5.0v TTL tolerant as well as tri-state isolated. Levels when any GPIO pin is used either as an input or as an output should again operate at nominal 3.3v TTL levels, thus expect "High" Voltage of 2.0 volts, threshold of 1.4v and "Low" voltage of 0.8v.

The maximum LCD Resolution supported must be at least 1440x900 @ 60fps, however there is no restriction on reducing the number of bits per pixel (to 8bpp or even to monochrome) if a particular low-cost SoC has severe video bandwidth limitations in achieving that resolution.

Table of EOMA-CF pinouts

Row 1 Row 2
* 1 LCD Pixel Data bit 3 (Red3) * 26 LCD Pixel Data bit 4 (Red4)
* 2 LCD Pixel Data bit 5 (Red5) * 27 LCD Pixel Data bit 6 (Red6)
* 3 LCD Pixel Data bit 7 (Red7) * 28 LCD Pixel Data bit 11 (Green3)
* 4 LCD Pixel Data bit 12 (Green4) * 29 LCD Pixel Data bit 13 (Green5)
* 5 LCD Pixel Data bit 14 (Green6) * 30 LCD Pixel Data bit 15 (Green7)
* 6 LCD Pixel Data bit 19 (Blue3) * 31 LCD Pixel Data bit 20 (Blue4)
* 7 LCD Pixel Data bit 21 (Blue5) * 32 LCD Pixel Data bit 22 (Blue6)
* 8 LCD Pixel Data bit 23 (Blue7) * 33 LCD Pixel Clock
* 9 GROUND * 34 GROUND
* 10 GPIO (0) / SDMMC-D3 * 35 GPIO (1) / SDMMC-D2
* 11 GPIO (2) / UART-TX * 36 GPIO (3) / UART-RX
* 12 GPIO (4) / SDMMC-CMD * 37 GPIO (5) / SDMMC-CLK
* 13 GPIO (6) / SDMMC-D0 * 38 GPIO (7) / SDMMC-D1
* 14 I2C Clock (SCL) * 39 I2C Data (SDA)
* 15 GPIO (10) / PWM * 40 LCD Vertical Synchronization
* 16 LCD Horizontal Synchronization * 41 LCD Pixel data enable (TFT) output
* 17 GPIO (12) / SPI_MISO * 42 GPIO (13) / SPI_MOSI
* 18 GPIO (14) / SPI_SCK * 43 GPIO (15) / EINT1
* 19 ---- not used ---- / USB3 StdA_SSRX- * 44 ---- not used ---- / USB3 StdA_SSRX+
* 20 ---- not used ---- / USB3 StdA_SSTX- * 45 ---- not used ---- / USB3 StdA_SSTX+
* 21 USB2 (Data-) * 46 USB2 (Data+)
* 22 PWR (5.0V) * 47 PWR (5.0v)
* 23 GPIO (11) / EINT0 * 48 VREF-TTL (GPIO TTL Voltage Reference)
* 24 GROUND * 49 GROUND
* 25 2nd USB2 (Data+) * 50 2nd USB2 (Data-)

Example CPU Card

A10 compact flash.png

This example CPU Card shows what is possible. It comprises an Allwinner A10 (Cortex A8), 2 DDR RAM ICs, 2 NAND Flash ICs, an AXP209 PMIC, an RTL8120 10/100 Ethernet PHY, yet leaves enough room for Micro-HDMI, USB-OTG and a Headphone socket. Missing from this diagram is where to put a MicroSD slot (hence the "under development" sign on this page). Potentially it could go on the underneath side (BOTTOM).

Prevention of insertion of standard CF Cards

To stop EOMA/CF cards from being inserted into standard CF slots, it will probably be necessary for the EOMA/CF cards to be a little bit thicker than standard CF cards, and potentially slightly wider at the very end (nearest the sockets). This would limit the number of sockets that could be used, however examination of some of 3M's sockets shows that the ejector mechanism is only down one side.