Embedded Open Modular Architecture/CompactFlash
page under development. this standard is virtually identical to EOMA-68 except that the 24-pin RGB/TTL has been replaced by single-channel LVDS.
the disadvantage of single-channel LVDS is that it is not sufficient to drive resolutions above 1280x1024 @ 75hz (24-bit) but if a lower refresh rate (40hz, 30hz) is acceptable, and/or a lower bitrate (18-bit) then it is possible to drive 1920x1080 at about 60hz for 18-bit or 47hz for 24-bit.
this standard is primarily designed for ultra-low-cost systems as well as those where space is at a premium. because of this, specifying MIPI as the LCD standard would be inappropriate, whereas many SoCs now have single-channel or in some case dual-channel LVDS available as standard. even in cases where the SoC does not have LVDS, a low-cost RGB/TTL to LVDS IC is available such as the [TI SN75LVDS83b](http://www.ti.com/product/sn75lvds83).
the edge of the CF card can have as many connectors as will fit into a 43mm width. Micro-HDMI Type D, USB-OTG and a 2.5mm 4-pin Headphone Jack can be considered. A MicroSD slot could be placed on one of the side edges (requiring the module to be removed and switched off in order to access it, as is the case with most mobile phones).
TODO: ensure no clash with power pins http://pinouts.ru/Memory/CompactFlash_pinout.shtml
These pinouts make no attempt to be electrically or electronically compatible with the existing CompactFlash standard. 16 GPIO pins, Single-channel LVDS for LCD, USB2, I2C, 10/100/1000 Ethernet and SATA-II interfaces are included in the Version 1.0 specification. Note: USB2, SATA-II and Ethernet must support auto-negotiation, and must support the lower capabilities (USB 1, USB 1.1, SATA-I, 10/100 Ethernet). Higher speeds and capabilities are optional.
Two 5.0v power inputs must be provided: all pins are rated at 0.5 amps, so the maximum power dissipation is limited to 5 watts. Design consideration: please note that to ensure that thermal dissipation in an enclosed fanless situation is not exceeded, a maximum of 3.5 watts should be respected. Most systems will not have active cooling.
All High-speed signals (LVDS, USB2, Ethernet, SATA-II) are balanced lines that are still separated using GND or Power pins. All other pins are low frequency. The sixteen GPIO pins are available, for general-purpose bi-directional use of digital data only.
The typical voltages of the LVDS LCD lines should be compatible with the LVDS output from a Texas Instruments SN75LVDS83b, i.e. 1.25V +/- 0.125V, and the peak-to-peak common-mode output voltage around 150mV, as illustrated in Figure 3 of the SN75LVDS83b datasheet.
Also, because the GPIO pins can be reconfigured individually bi-directional for any digital purposes, they *must* be made to be 5V TTL tolerant and tri-state isolated, and Motherboards also must be 5.0v TTL tolerant as well as tri-state isolated. Levels when any GPIO pin is used either as an input or as an output should again operate at nominal 3.3v TTL levels, thus expect "High" Voltage of 2.0 volts, threshold of 1.4v and "Low" voltage of 0.8v.
The option to use Gigabit Ethernet is also available, if a given system has it. If, however, a particular system does not have Gigabit Ethernet, the pins must not be used for other purposes, and must be left unconnected. This is to ensure that automatic negotiation of 100/1000 Ethernet occurs correctly.
Table of EOMA-CF pinouts
|Row 1||Row 2|
|* 1 RIN 0- Negative LVDS differential data output 0||* 26 RIN 0+ Positive LVDS differential data output 0|
|* 2 RIN 1- Negative LVDS differential data output 0||* 27 RIN 1+ Positive LVDS differential data output 0|
|* 3 RIN 2- Negative LVDS differential data output 0||* 28 RIN 2+ Positive LVDS differential data output 0|
|* 4 CLKIN- Negative LVDS differential clock output 0||* 29 CLKIN+ Positive LVDS differential clock output 0|
|* 5 RIN 0- Negative LVDS differential data output 1||* 30 RIN 0+ Positive LVDS differential data output 1|
|* 6 RIN 1- Negative LVDS differential data output 1||* 31 RIN 1+ Positive LVDS differential data output 1|
|* 7 RIN 2- Negative LVDS differential data output 1||* 32 RIN 2+ Positive LVDS differential data output 1|
|* 8 CLKIN- Negative LVDS differential clock output 1||* 33 CLKIN+ Positive LVDS differential clock output 1|
|* 9 GROUND||* 34 GROUND|
|* 10 ---- not used ---- / 1000 Eth BI_DD+||* 35 ---- not used ---- / 1000 Eth BI_DD-|
|* 11 10/100 Ethernet (RX+) / 1000 Eth BI_DB+||* 36 10/100 Ethernet (RX-) / 1000 Eth BI_DB-|
|* 12 10/100 Ethernet (TX+) / 1000 Eth BI_DA+||* 37 10/100 Ethernet (TX-) / 1000 Eth BI_DA-|
|* 13 ---- not used ---- / 1000 Eth BI_DC+||* 38 ---- not used ---- / 1000 Eth BI_DC-|
|* 14 I2C Clock (SCL)||* 39 I2C Data (SDA)|
|* 15 GPIO (0)||* 40 GPIO (1)|
|* 16 GPIO (2)||* 41 GPIO (3)|
|* 17 GPIO (4)||* 42 GPIO (5)|
|* 18 GPIO (6)||* 43 GPIO (7)|
|* 19 ---- not used ---- / USB3 StdA_SSRX-||* 44 ---- not used ---- / USB3 StdA_SSRX+|
|* 20 ---- not used ---- / USB3 StdA_SSTX-||* 45 ---- not used ---- / USB3 StdA_SSTX+|
|* 21 USB2 (Data-)||* 46 USB2 (Data+)|
|* 22 PWR (5.0V)||* 47 PWR (5.0v)|
|* 23 SATA-II Transmit (A+)||* 48 SATA-II Transmit (A-)|
|* 24 GROUND||* 49 GROUND|
|* 25 SATA-II Receive (B+)||* 50 SATA-II Receive (B-)|
Example CPU Card
This example CPU Card shows what is possible. It comprises an Allwinner A10 (Cortex A8), 2 DDR RAM ICs, 2 NAND Flash ICs, an AXP209 PMIC, an RTL8120 10/100 Ethernet PHY, yet leaves enough room for Micro-HDMI, USB-OTG and a Headphone socket. Missing from this diagram is where to put a MicroSD slot (hence the "under development" sign on this page). Potentially it could go on the underneath side (BOTTOM).
Prevention of insertion of standard CF Cards
To stop EOMA/CF cards from being inserted into standard CF slots, it will probably be necessary for the EOMA/CF cards to be a little bit thicker than standard CF cards, and potentially slightly wider at the very end (nearest the sockets). This would limit the number of sockets that could be used, however examination of some of 3M's sockets shows that the ejector mechanism is only down one side.