Difference between revisions of "Embedded Open Modular Architecture/EOMA-26"

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(Created page with "=== Table of EOMA-CF pinouts === {|cellpadding="2" cellspacing="0" border="1" width="60%" !style="width:50%"|Row 1 !style="width:50%"|Row 2 |- |* 1 RIN 0- Negative LVDS d...")
 
(Table of EOMA-26 pinouts)
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=== Table of EOMA-CF pinouts ===
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=== Table of EOMA-26 pinouts ===
 
{|cellpadding="2" cellspacing="0" border="1" width="60%"
 
{|cellpadding="2" cellspacing="0" border="1" width="60%"
 
!style="width:50%"|Row 1
 
!style="width:50%"|Row 1
 
!style="width:50%"|Row 2
 
!style="width:50%"|Row 2
 
|-
 
|-
|* 1    RIN 0-  Negative LVDS differential data output 0
+
|* 1     GROUND
|* 26    RIN 0+  Positive LVDS differential data output 0
+
|* 14     RIN 0-  Negative LVDS differential data output
 
|-
 
|-
|* 2     RIN 1- Negative LVDS differential data output 0
+
|* 2     USB2 (Data-)
|* 27    RIN 1+  Positive LVDS differential data output 0
+
|* 15    RIN 1+  Positive LVDS differential data output
 
|-
 
|-
|* 3    RIN 2-  Negative LVDS differential data output 0
+
|* 3     USB2 (Data+)
|* 28    RIN 2+  Positive LVDS differential data output 0
+
|* 16     RIN 1-  Negative LVDS differential data output
 
|-
 
|-
|* 4     CLKIN-  Negative LVDS differential clock output 0
+
|* 4     PWR (5.0V)
|* 29    CLKIN+  Positive LVDS differential clock output 0
+
|* 17    RIN 2+  Positive LVDS differential data output
 
|-
 
|-
|* 5   RIN 0-  Negative LVDS differential data output 1
+
|* 5     GPIO2 / UART_TX
|* 30  RIN 0+ Positive LVDS differential data output 1
+
|* 18    RIN 2- Negative LVDS differential data output
 
|-
 
|-
|* 6      RIN 1-  Negative LVDS differential data output 1
+
|* 6      GPIO3 / UART_RX
|* 31    RIN 1+  Positive LVDS differential data output 1
+
|* 19    PWR (5.0V)
 
|-
 
|-
|* 7      RIN 2-  Negative LVDS differential data output 1
+
|* 7      I2C Clock (SCL)
|* 32     RIN 2+  Positive LVDS differential data output 1
+
|* 20     SDC-CMD
 
|-
 
|-
|* 8     CLKIN-  Negative LVDS differential clock output 1
+
|* 8     I2C Data (SDA)
|* 33    CLKIN+  Positive LVDS differential clock output 1
+
|* 21    SDC-CLK
 
|-
 
|-
|* 9 GROUND
+
|* 9     GPIO0
|* 34 GROUND
+
|* 22    GPIO4 / SDC-3
 
|-
 
|-
|* 10 GPIO (0)
+
|* 10     GPIO1
|* 35 GPIO (1)
+
|* 23    GPIO5 / SDC-2
 
|-
 
|-
|* 11 GPIO (2)
+
|* 11     CLKIN+  Positive LVDS differential clock output
|* 36 GPIO (3)
+
|* 24    GPIO6 / SDC-1
 
|-
 
|-
|* 12 GPIO (4)
+
|* 12     CLKIN-  Negative LVDS differential clock output
|* 37 GPIO (5)
+
|* 25    SDC-0
 
|-
 
|-
|* 13 GPIO (6)
+
|* 13     RIN 0+ Positive LVDS differential data output
|* 38 GPIO (7)
+
|* 26    GND
|-
+
|* 14 I2C Clock (SCL)
+
|* 39 I2C Data (SDA)
+
|-
+
|* 15 ---- not used ---- / 1000 Eth BI_DD+
+
|* 40 ---- not used ---- / 1000 Eth BI_DD-
+
|-
+
|* 16 10/100 Ethernet (RX+) / 1000 Eth BI_DB+
+
|* 41 10/100 Ethernet (RX-) / 1000 Eth BI_DB-
+
|-
+
|* 17 10/100 Ethernet (TX+) / 1000 Eth BI_DA+
+
|* 42 10/100 Ethernet (TX-) / 1000 Eth BI_DA-
+
|-
+
|* 18 ---- not used ---- / 1000 Eth BI_DC+
+
|* 43 ---- not used ---- / 1000 Eth BI_DC-
+
|-
+
|* 19 ---- not used ---- / USB3 StdA_SSRX-
+
|* 44 ---- not used ---- / USB3 StdA_SSRX+
+
|-
+
|* 20 ---- not used ---- / USB3 StdA_SSTX-
+
|* 45 ---- not used ---- / USB3 StdA_SSTX+
+
|-
+
|* 21 USB2 (Data-)
+
|* 46 USB2 (Data+)
+
|-
+
|* 22 PWR (5.0V)
+
|* 47 PWR (5.0v)
+
|-
+
|* 23 SATA-II Transmit (A+)
+
|* 48 SATA-II Transmit (A-)
+
|-
+
|* 24 GROUND
+
|* 49 GROUND
+
|-
+
|* 25 SATA-II Receive (B+)
+
|* 50 SATA-II Receive (B-)
+
 
|}
 
|}

Revision as of 20:27, 29 June 2013

Table of EOMA-26 pinouts

Row 1 Row 2
* 1 GROUND * 14 RIN 0- Negative LVDS differential data output
* 2 USB2 (Data-) * 15 RIN 1+ Positive LVDS differential data output
* 3 USB2 (Data+) * 16 RIN 1- Negative LVDS differential data output
* 4 PWR (5.0V) * 17 RIN 2+ Positive LVDS differential data output
* 5 GPIO2 / UART_TX * 18 RIN 2- Negative LVDS differential data output
* 6 GPIO3 / UART_RX * 19 PWR (5.0V)
* 7 I2C Clock (SCL) * 20 SDC-CMD
* 8 I2C Data (SDA) * 21 SDC-CLK
* 9 GPIO0 * 22 GPIO4 / SDC-3
* 10 GPIO1 * 23 GPIO5 / SDC-2
* 11 CLKIN+ Positive LVDS differential clock output * 24 GPIO6 / SDC-1
* 12 CLKIN- Negative LVDS differential clock output * 25 SDC-0
* 13 RIN 0+ Positive LVDS differential data output * 26 GND