Embedded Open Modular Architecture/PCMCIA

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PCMCIA form-factor Open Modular Architecture

This page describes the specification for re-purposing of the PCMCIA interface and form-factor as a portable Embedded Computing Module. Mass-volume "Lowest Common Denominator" interfaces have been chosen, all of which have existed for over a decade, but are low-power enough to be standard across virtually all mass-produced powerful Embedded CPUs. These interfaces are: 24-pin RGB/TTL (for LCD Panels), I2C, USB2, 10/100 Ethernet, and SATA-II. The interfaces have been specifically chosen because they are either essential or they are multi-purpose buses. The only interface which is not particularly common on mass-produced powerful Embedded CPUs is SATA-II: this can be constructed from a USB-to-SATA converter IC such as the Genesys Logic GL831A.

Pinouts (Version 1.0)

These pinouts make no attempt to be electrically or electronically compatible with the legacy PCMCIA standard. 16 GPIO pins, 24-pin RGB/TTL, USB2, I2C, 10/100 Ethernet and SATA-II interfaces are included in the Version 1.0 specification.

Two 5.0v power inputs must be provided: all pins are rated at 0.5 amps, so the maximum power dissipation is limited to 5 watts. This limit is deliberate, to ensure that thermal dissipation in an enclosed fanless situation is not exceeded.

All High-speed signals (USB2, Ethernet, SATA-II) are balanced lines that are still separated using GND pins. All other pins are low frequency, with the exception of the LCD Pixel Clock and Pixel Data pins, which could go as high as 125mhz for 1920x1080 @ 60fps (not recommended). The sixteen GPIO pins are available, for general-purpose use.

  1. LCD Pixel Clock
  2. LCD Pixel data enable (TFT) output
  3. LCD Horizontal Synchronization
  4. LCD Vertical Synchronization
  5. LCD Pixel Data bit 0 (Red0)
  6. LCD Pixel Data bit 1 (Red1)
  7. LCD Pixel Data bit 2 (Red2)
  8. LCD Pixel Data bit 3 (Red3)
  9. LCD Pixel Data bit 4 (Red4)
  10. LCD Pixel Data bit 5 (Red5)
  11. LCD Pixel Data bit 6 (Red6)
  12. LCD Pixel Data bit 7 (Red7)
  13. LCD Pixel Data bit 8 (Green0)
  14. LCD Pixel Data bit 9 (Green1)
  15. LCD Pixel Data bit 10 (Green2)
  16. LCD Pixel Data bit 11 (Green3)
  17. LCD Pixel Data bit 12 (Green4)
  18. LCD Pixel Data bit 13 (Green5)
  19. LCD Pixel Data bit 14 (Green6)
  20. LCD Pixel Data bit 15 (Green7)
  21. LCD Pixel Data bit 16 (Blue0)
  22. LCD Pixel Data bit 17 (Blue1)
  23. LCD Pixel Data bit 18 (Blue2)
  24. LCD Pixel Data bit 19 (Blue3)
  25. LCD Pixel Data bit 20 (Blue4)
  26. LCD Pixel Data bit 21 (Blue5)
  27. LCD Pixel Data bit 22 (Blue6)
  28. LCD Pixel Data bit 23 (Blue7)
  29. GROUND
  30. GROUND
  31. 10/100 Ethernet (TX+)
  32. 10/100 Ethernet (TX-)
  33. 10/100 Ethernet (RX+)
  34. 10/100 Ethernet (RX-)
  35. GROUND
  36. GROUND
  37. USB2 (Data+)
  38. USB2 (Data-)
  39. GROUND
  40. GROUND
  41. I2C Clock (SCL)
  42. I2C Data (SDA)
  43. PWR (5.0V)
  44. PWR (5.0v)
  45. GPIO (0)
  46. GPIO (1)
  47. GPIO (2)
  48. GPIO (3)
  49. GPIO (4)
  50. GPIO (5)
  51. GPIO (6)
  52. GPIO (7)
  53. GPIO (8)
  54. GPIO (9)
  55. GPIO (10)
  56. GPIO (11)
  57. GPIO (12)
  58. GPIO (13)
  59. GPIO (14)
  60. GPIO (15)
  61. GROUND
  62. GROUND
  63. SATA-II Transmit (A+)
  64. SATA-II Transmit (A-)
  65. GROUND
  66. GROUND
  67. SATA-II Receive (B+)
  68. SATA-II Receive (B-)

Start-up procedure

It is recommended that all pins be disabled (floating tri-state). I2C Bus Master is then enabled, to search for an I2C EEPROM. This EEPROM contains Linux Kernel "Device Tree" data, which specifies the actual pin-outs.