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The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy. Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the TLB when a memory access occurs. When memory translation is disabled, storage attributes are maintained in storage attribute control registers. A zone protection register (ZPR) is provided to allow system software to override the TLB access controls without requiring the manipulation of individual TLB entries.
 
The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy. Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the TLB when a memory access occurs. When memory translation is disabled, storage attributes are maintained in storage attribute control registers. A zone protection register (ZPR) is provided to allow system software to override the TLB access controls without requiring the manipulation of individual TLB entries.
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[[Category:PowerPC]]

Revision as of 06:11, 28 October 2011

PowerPC

TLB

Home : Products & Services : System Resources : Processor Central : PowerPC : Architecture : MMU

PowerPC Architecture - Memory Management Unit (MMU)


The PowerPC™ 405 supports 4 GB of flat (non-segmented) address space. The Memory Management Unit (MMU) provides Address Translation, Protection Functions, and Storage Attribute Control for this address space. The MMU supports demand-paged virtual memory using multiple page sizes of 1 KB up to16 MB. When supported by system software, the MMU provides the following functions:

   * Translation of the 4 GB logical address space into a physical address space
   * Independent enabling of instruction translation and protection from that of data translation and protection
   * Page-level access control using the translation mechanism
   * Software control over the page replacement strategy
   * Additional protection control using zones
   * Storage attributes for cache policy and speculative memory access control

The Translation Look-aside Buffer (TLB) is used to control memory translation and protection. Each one of its 64 entries specifies a page translation. It is fully associative and can simultaneously hold translations for any combination of page sizes. To prevent TLB contention between data and instruction accesses, a 4-entry instruction and an 8-entry data shadow TLB are maintained by the processor transparently to the software. Software manages the initialization and replacement of TLB entries.

The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy. Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the TLB when a memory access occurs. When memory translation is disabled, storage attributes are maintained in storage attribute control registers. A zone protection register (ZPR) is provided to allow system software to override the TLB access controls without requiring the manipulation of individual TLB entries.