Flameman/PowerPC - Revision history

Legacy at 11:39, 17 April 2012

2012-04-17T11:39:29Z

Legacy at 11:38, 17 April 2012

2012-04-17T11:38:59Z

Legacy: /* Info */

2012-04-17T11:38:20Z

‎Info

Legacy: /* Features */

2012-04-17T11:37:29Z

‎Features

Legacy: /* Appendix References */

2012-04-17T11:13:57Z

‎Appendix References

Legacy: /* TLB */

2012-04-17T11:05:42Z

‎TLB

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Cschalle: Add category

2011-10-28T06:11:48Z

Add category

Flameman: Created page with '= PowerPC = == TLB == Home : Products & Services : System Resources : Processor Central : PowerPC : Architecture : MMU PowerPC Architecture - Memory Management Unit (MMU) …'

2010-05-31T08:01:19Z

Created page with '= PowerPC = == TLB == Home : Products & Services : System Resources : Processor Central : PowerPC : Architecture : MMU PowerPC Architecture - Memory Management Unit (MMU) …'

New page

= PowerPC =

== TLB ==

Home : Products & Services : System Resources : Processor Central : PowerPC : Architecture : MMU

PowerPC Architecture - Memory Management Unit (MMU)

The PowerPC™ 405 supports 4 GB of flat (non-segmented) address space. The Memory Management Unit (MMU) provides Address Translation, Protection Functions, and Storage Attribute Control for this address space. The MMU supports demand-paged virtual memory using multiple page sizes of 1 KB up to16 MB. When supported by system software, the MMU provides the following functions:

* Translation of the 4 GB logical address space into a physical address space
* Independent enabling of instruction translation and protection from that of data translation and protection
* Page-level access control using the translation mechanism
* Software control over the page replacement strategy
* Additional protection control using zones
* Storage attributes for cache policy and speculative memory access control

The Translation Look-aside Buffer (TLB) is used to control memory translation and protection. Each one of its 64 entries specifies a page translation. It is fully associative and can simultaneously hold translations for any combination of page sizes. To prevent TLB contention between data and instruction accesses, a 4-entry instruction and an 8-entry data shadow TLB are maintained by the processor transparently to the software. Software manages the initialization and replacement of TLB entries.

The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy. Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the TLB when a memory access occurs. When memory translation is disabled, storage attributes are maintained in storage attribute control registers. A zone protection register (ZPR) is provided to allow system software to override the TLB access controls without requiring the manipulation of individual TLB entries.

← Older revision		Revision as of 11:39, 17 April 2012
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−	= PowerPC =	+	= PowerPC (to be fixed) =

	== TLB ==		== TLB ==

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−	== Book-E coverage ==	+	== Book-E coverage (to be fixed, soon) ==

	In Book-E, PPC Instructions are classified as following;		In Book-E, PPC Instructions are classified as following;

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 === Info ===
-* CPU Performance 133-266MHz - Features GPIO, PCI, SRAM Memory Controller
+* CPU Performance 133-266MHz
-* Datasheet: {{pdf|ppc405gp.pdf | ppc405gp}}
+* Features GPIO, PCI, SRAM Memory Controller
-* [https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/405GP_GPR/PPC405GP_UM2005_v1_02.pdf User's manual|User's Manual]
+* A fast, flexible solution for embedded developers.
-* Errata: {{pdf|ppc405gp-errata.pdf|ppc405gp-errata}}
-−
 A fast, flexible solution for embedded developers.
 === General Description ===

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 === Features ===
-* On-chip SDRAM Controller
 * Contains separate 32-byte read and 128-byte write buffers
 * Programmable address mapping
-* External Peripheral Controller
 * Supports ROM, EPROM, SRAM
 * Flash and slave peripheral I/O devices
 * 8, 16, 32-bit external data bus width
 * Programmable address mapping
 * External Bus Master Controller - Allows external masters to access SDRAM and PCI
-* DMA Controller, 4 independent channels, Supports transfers between SDRAM, PCI, internal UARTs, and devices on the external peripheral bus
-* PCI Interface, * 32-bit PCI V2.2 compatible, Synchronous and asynchronous operation
+DMA Controller
-* Internal PCI arbiter supports six PCI masters, Supports external arbitration
+* 4 independent channels
-* On-chip Ethernet Support, 10/100 MAC, Dedicated DMA controller
+* Supports transfers between SDRAM, PCI, internal UARTs, and devices on the external peripheral bus
-** CodePack Decompression
-*** Stores instructions in memory in compressed format
+PCI Interface
-*** Improves code density by up to 40%
+* 32-bit PCI V2.2 compatible
-** Other On-chip Peripherals
+* Synchronous and asynchronous operation
-*** 2 serial ports
+* Internal PCI arbiter supports six PCI masters
-*** Master and slave IIC controller
+* Supports external arbitration
-*** Up to 24 general purpose I/Os
-*** Interrupt controller including up to 13 external interrupts
+On-chip Ethernet Support

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 * 440x4_um.pdf PPC440 CPU Core Users Manual, SA14-2523-02 July 18, 2002
 * booke_rm.pdf Book E: Enhanced PowerPC Architecture, Version 1.0 May 7, 2002
 [[Category:PowerPC]]

← Older revision		Revision as of 06:11, 28 October 2011
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	The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy. Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the TLB when a memory access occurs. When memory translation is disabled, storage attributes are maintained in storage attribute control registers. A zone protection register (ZPR) is provided to allow system software to override the TLB access controls without requiring the manipulation of individual TLB entries.		The PowerPC 405 includes instructions for managing TLB entries by software running in privileged mode. This capability gives significant control to system software over the implementation of a page replacement strategy. Storage attributes are provided to control access of memory regions. When memory translation is enabled, storage attributes are maintained on a page basis and read from the TLB when a memory access occurs. When memory translation is disabled, storage attributes are maintained in storage attribute control registers. A zone protection register (ZPR) is provided to allow system software to override the TLB access controls without requiring the manipulation of individual TLB entries.
		+
		+	[[Category:PowerPC]]