Difference between revisions of "Flameman/eltek"

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* a.m.p. http://en.wikipedia.org/wiki/Asymmetric_multiprocessing
 
* a.m.p. http://en.wikipedia.org/wiki/Asymmetric_multiprocessing
 
* s.m.p. http://en.wikipedia.org/wiki/Symmetric_multiprocessing
 
* s.m.p. http://en.wikipedia.org/wiki/Symmetric_multiprocessing
 
+
* n.u.m.a. there is also an other working schema, called "numa", see[[Flameman/numa]], useful with a great amount of cpu (cpu >> 8)
 
+
there is also an other working schema, called [[Flameman/numa]], useful with a great amount of cpu (cpu >> 8)
+
  
  
  
 
it seems that the dual-CPU V460 is featuring a symmetrical architecture allowing the two 68060 CPUs to operate as either tightly-coupled coprocessors sharing the same operating system and peripherals or as two independent CPUs running separate operating systems across separate I/O channels.
 
it seems that the dual-CPU V460 is featuring a symmetrical architecture allowing the two 68060 CPUs to operate as either tightly-coupled coprocessors sharing the same operating system and peripherals or as two independent CPUs running separate operating systems across separate I/O channels.
 +
If this info is right it should be possible to assign different interrupt level schemes to each CPU via a programmable interrupt control register.
 +
In all of these possible arrangements, the dual CPU V460 Series can provide full multi-ported memory access by both CPUs, the VMEbus, and both EZ-bus modules with varying levels of memory protection as required.

Revision as of 09:55, 16 July 2011

For more interesting projects done by Flameman, be sure to checkout his project index


EUROCOM 27???

doc???

  • CPU: dual 33 MHz 68060 processors
  • ram: 64 Mbytes, DRAM
  • lan: Ethernet
  • interface: Graphics, SCSI-2, VME 32/64?
  • OS: comes with OS-9, LynxOS, pSOS+, PDOS, VxWorks


  • Memory is provided on a piggyback module allowing it to be easily upgraded
  • Up to 4 Mbytes of FLASH
  • Supports ELTEC's LEB mezzanine bus


is this system (hw-2x68060/vxworks)s.m.p. or a.m.p. ?


it seems that the dual-CPU V460 is featuring a symmetrical architecture allowing the two 68060 CPUs to operate as either tightly-coupled coprocessors sharing the same operating system and peripherals or as two independent CPUs running separate operating systems across separate I/O channels. If this info is right it should be possible to assign different interrupt level schemes to each CPU via a programmable interrupt control register. In all of these possible arrangements, the dual CPU V460 Series can provide full multi-ported memory access by both CPUs, the VMEbus, and both EZ-bus modules with varying levels of memory protection as required.