Flameman/eltek - Revision history

Legacy: /* uart calbe pin out (tested and working */

2012-04-17T12:27:52Z

‎uart calbe pin out (tested and working

Flameman: /* Bootstrap */

2012-03-25T20:44:38Z

‎Bootstrap

Flameman: /* Bootstrap */

2012-03-25T20:43:43Z

‎Bootstrap

Cschalle: Add categories

2011-10-28T07:30:24Z

Add categories

Flameman: /* vme backplane */

2011-07-16T11:57:58Z

‎vme backplane

Flameman at 10:34, 16 July 2011

2011-07-16T10:34:22Z

Flameman at 10:25, 16 July 2011

2011-07-16T10:25:06Z

Flameman: /* vme backplane */

2011-07-16T10:23:50Z

‎vme backplane

Flameman: /* power needed */

2011-07-16T10:23:35Z

‎power needed

Flameman: /* Info = */

2011-07-16T10:18:52Z

‎Info =

← Older revision		Revision as of 12:27, 17 April 2012
Line 290:		Line 290:

	</pre>		</pre>
		+
		+
		+
		+	== Category ==
		+
		+	[[Category: 68k]]
		+	[[Category: 68060]]

← Older revision		Revision as of 20:44, 25 March 2012
Line 136:		Line 136:
	either 68060 can execute from either or both of the EPROMs.		either 68060 can execute from either or both of the EPROMs.

		+
		+	== about system fail ==
		+
		+	<pre>
		+
		+	* * * * * * * * * * * * * * * * * * * * * * * *
		+	ACFail\
		+	* * * * * * * * * * * * * * * * * * * * * * * *
		+
		+
		+	The two red LEDs indicate the run status of the board:
		+
		+
		+
		+	Fail Indicates the SysFail status of the board.
		+	When the CPU is reset (either by the VMEbus
		+	SysRes\ line or the front panel RESET toggle),
		+	the Fail LED turns on
		+	and the board drives the VME SysFail\ signal.
		+	During normal operation the system boot software
		+	clears this condition shortly after RESET.
		+	The SysFail LED and driver signal are cleared
		+	by performing a write of a 0C to
		+	the Primary Mode register at 0XFE38 0003.
		+	The program may also turn this LED on
		+	(i.e. assert SysFail on the VMEbus)
		+	by writing a 04 to 0xFE38 0003.
		+
		+	Halt On single-68060 model boards, this LED provides
		+	a visual indication that the on-board CPU has HALTed.
		+	On dual-68060 boards, this LED indicates that
		+	one or both CPUs has HALTed. If only one CPU has HALTed,
		+	it is possible to identify which one by also looking at
		+	the X and Y LEDs.
		+	Generally, the LED for the HALTed CPU is NOT lit.
		+	However, this indication is very dependent on
		+	the application being run
		+	and how closely coupled the two CPUs are operating
		+
		+	Bus error
		+	time out
		+	Generates a bus error time-out signal if one or
		+	both of the VMEbus data strobes remain asserted
		+	for longer than a specific interval that can be set
		+	under software control.
		+	System reset
		+	generator
		+	Generates a VMEbus reset signal upon system
		+	power-up, upon a board-level reset, and 100
		+	microseconds after the VME ACFail signal is
		+	asserted
		+	</pre>

	== uart calbe pin out (tested and working ==		== uart calbe pin out (tested and working ==

@@ Line 136: / Line 136: @@
 either 68060 can execute from either or both of the EPROMs.
-[[Category:Flameman]]
-[[Category:Development Boards]]
+== uart calbe pin out (tested and working ==

← Older revision		Revision as of 07:30, 28 October 2011
Line 135:		Line 135:
	except for the first 3 fetches in boot state in which CPU-X fetches from PROM0 and CPU-Y fetches from PROM1		except for the first 3 fetches in boot state in which CPU-X fetches from PROM0 and CPU-Y fetches from PROM1
	either 68060 can execute from either or both of the EPROMs.		either 68060 can execute from either or both of the EPROMs.
		+
		+	[[Category:Flameman]]
		+	[[Category:Development Boards]]

← Older revision		Revision as of 11:57, 16 July 2011
Line 47:		Line 47:

	== vme backplane ==		== vme backplane ==
		+
		+	=== Pinout ===
		+
		+
		+	VMEbus connector pinouts
		+	VMEbus P1 VMEbus P2
		+	<pre>
		+	Pin Row A Row B Row C Pin Row A * Row B Row C**
		+	1 D00 BBsy\ D08 1 P4 - pin B32 +5v P4 - pin A32
		+	2 D01 BClr\ D09 2 P4 - pin B31 Gnd P4 - pin A31
		+	3 D02 ACFail\ D10 3 P4 - pin B30 reserved P4 - pin A30
		+	4 D03 BG0In\ D11 4 P4 - pin B29 A24 P4 - pin A29
		+	5 D04 BG0Out\ D12 5 P4 - pin B28 A25 P4 - pin A28
		+	6 D05 BG1In\ D13 6 P4 - pin B27 A26 P4 - pin A27
		+	7 D06 BG1Out\ D14 7 P4 - pin B26 A27 P4 - pin A26
		+	8 D07 BG2In\ D15 8 P4 - pin B25 A28 P4 - pin A25
		+	9 Gnd BG2Out\ Gnd 9 P4 - pin B24 A29 P4 - pin A24
		+	10 SysClk BG3In\ Sysfail\ 10 P4 - pin B23 A30 P4 - pin A23
		+	11 Gnd BG3Out\ BErr\ 11 P4 - pin B22 A31 P4 - pin A22
		+	12 DS1\ BR0\ SysRes\ 12 P4 - pin B21 Gnd P4 - pin A21
		+	13 DS0\ BR1\ LWord\ 13 P4 - pin B20 +5v P4 - pin A20
		+	14 Write\ BR2\ AM5 14 P4 - pin B19 D16 P4 - pin A19
		+	15 Gnd BR3\ A23 15 P4 - pin B18 D17 P4 - pin A18
		+	16 DTAck\ AM0 A22 16 P4 - pin B17 D18 P4 - pin A17
		+	17 Gnd AM1 A21 17 P4 - pin B16 D19 P4 - pin A16
		+	18 AS\ AM2 A20 18 P4 - pin B15 D20 P4 - pin A15
		+	19 Gnd AM3 A19 19 P4 - pin B14 D21 P4 - pin A14
		+	20 IAck\ Gnd A18 20 P4 - pin B13 D22 P4 - pin A13
		+	21 IAckIn\ SerClk(1) A17 21 P4 - pin B12 D23 P4 - pin A12
		+	22 IAckOut\ SerDat\(1) A16 22 P4 - pin B11 Gnd P4 - pin A11
		+	23 AM4 Gnd A15 23 P4 - pin B10 D24 P4 - pin A10
		+	24 A07 IRQ7\ A14 24 P4 - pin B9 D25 P4 - pin A9
		+	25 A06 IRQ6\ A13 25 P4 - pin B8 D26 P4 - pin A8
		+	26 A05 IRQ5\ A12 26 P4 - pin B7 D27 P4 - pin A7
		+	27 A04 IRQ4\ A11 27 P4 - pin B6 D28 P4 - pin A6
		+	28 A03 IRQ3\ A10 28 P4 - pin B5 D29 P4 - pin A5
		+	29 A02 IRQ2\ A09 29 P4 - pin B4 D30 P4 - pin A4
		+	30 A01 IRQ1\ A08 30 P4 - pin B3 D31 P4 - pin A3
		+	31 -12v +5vStdby +12v 31 P4 - pin B2 Gnd P4 - pin A2
		+	32 +5v +5v +5v 32 P4 - pin B1 +5v P4 - pin A1
		+	</pre>
		+
		+	Notes: * This row of pins on P2 connect to the pin listed in row B of the EZ-bus connector (P4).
		+	** This row of pins on P2 connect to the pin listed in row A of the EZ-bus connector (P4).
		+

	=== !!!warning!!! ===		=== !!!warning!!! ===

← Older revision		Revision as of 10:34, 16 July 2011
Line 80:		Line 80:
	(P1-P2) chapter in Section 7.		(P1-P2) chapter in Section 7.
	</pre>		</pre>
		+
		+	== Bootstrap ==
		+
		+	On V460 Series dual-68060 models, the following boot architecture is
		+	used:
		+	* CPU-X executes from EPROM0 at 0xFE000000 to 0xFE0FFFFF
		+	* CPU-Y executes from EPROM1 at 0xFE400000 to 0xFE4FFFFF or 0xFD000000 to 0xFDFFFFFF
		+
		+	except for the first 3 fetches in boot state in which CPU-X fetches from PROM0 and CPU-Y fetches from PROM1
		+	either 68060 can execute from either or both of the EPROMs.

@@ Line 3: / Line 3: @@
 = Info =
-the board has been made be synergy microsystem
-it seems the board+bsp+vxworks has been sold as "EUROCOM 27xxx"
+The board has been made be synergy microsystem as V462 (dual processor) in V460 Series
 == Overview ==

@@ Line 47: / Line 47: @@
 == vme backplane ==
-=== !!!warning!!!
+=== !!!warning!!! ===
 <pre>
 Pin row B of the P2 backplane is defined

← Older revision		Revision as of 10:23, 16 July 2011
Line 43:		Line 43:
	* +5.0v ±5% = 6.4 amps (typical)		* +5.0v ±5% = 6.4 amps (typical)
	* -12.0v ±5% = 30 mA		* -12.0v ±5% = 30 mA
		+
		+
		+	== vme backplane ==
		+
		+	=== !!!warning!!!
		+	<pre>
		+	Pin row B of the P2 backplane is defined
		+	by VMEbus specifications and is bussed
		+	across the entire backplane. Pin rows A
		+	and C are user configured and, if con–
		+	nected at all, are normally connected to
		+	adjacent slots via wirewrap or special ca-
		+	bles.
		+	Because the P2 pinout may vary between
		+	backplanes or even slots in the same
		+	backplane, DO NOT INSTALL the V460
		+	Series into a system slot whose P2
		+	backplane is not compatible with the
		+	V460 Series’ P2 pin-out. Failure to
		+	observe this warning can cause the
		+	complete destruction of many on-board
		+	components and also voids the product
		+	warranty.
		+	The V460 Series pin-out meets standard
		+	VME specifications for row B, but rows A
		+	and C will vary according to the EZ-bus
		+	daughter module installed. Daughter
		+	board pinouts are shown in the
		+	associated daughter module manual. If
		+	no daughter module is present, P2 back-
		+	plane rows A and C are defined as no-
		+	connects.
		+	For a complete list of the V460 Series P2
		+	assignments, see the VMEbus connectors
		+	(P1-P2) chapter in Section 7.
		+	</pre>