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< Flameman
Revision as of 16:12, 15 May 2012 by Legacy (Talk | contribs)

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ALtera link


Asynchronous counter using Verilog

module counter( clk, count );
input clk;
output[3:0] count;

reg[3:0] count;
wire clk;

    count = 4'b0;

always @( negedge clk )
    count[0] <= ~count[0];

always @( negedge count[0] )
    count[1] <= ~count[1];

always @( negedge count[1] )
    count[2] <= ~count[2];

always @( negedge count[2] )
    count[3] <= ~count[3];