Flameman/m68ec0x0IDP - Revision history

Peter Huewe: Added to category 68k

2011-04-12T20:37:46Z

Added to category 68k

Peter Huewe: Added some text to Flamemans index link

2011-04-12T20:21:54Z

Added some text to Flamemans index link

Flameman at 19:29, 3 December 2009

2009-12-03T19:29:28Z

Flameman: /* ebook */

2009-10-25T10:19:59Z

‎ebook

Flameman: /* Should I assert RESET* on the MC68000 without asserting HALT* as well? */

2009-10-25T10:17:01Z

‎Should I assert RESET* on the MC68000 without asserting HALT* as well?

Flameman: /* Is it okay to tie the HALT* and RESET* lines together on the MC68000 together? */

2009-10-25T10:16:42Z

‎Is it okay to tie the HALT* and RESET* lines together on the MC68000 together?

Flameman: /* What is the interrupt latency for the MC68000 family? */

2009-10-25T10:16:05Z

‎What is the interrupt latency for the MC68000 family?

Flameman: /* If BR* is asserted before RESET* negates, when will the MC68HC000 take control of the bus? */

2009-10-25T10:15:21Z

‎If BR* is asserted before RESET* negates, when will the MC68HC000 take control of the bus?

Flameman: /* What is the state of AS* during reset on the MC68000 and how long after reset before AS* becomes valid? */

2009-10-25T10:14:52Z

‎What is the state of AS* during reset on the MC68000 and how long after reset before AS* becomes valid?

Flameman: /* What is the difference between an MC68000 and an MC68008? */

2009-10-25T10:14:19Z

‎What is the difference between an MC68000 and an MC68008?

← Older revision		Revision as of 20:37, 12 April 2011
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	If BR* is asserted when the MC68HC000 comes out of reset, it will assert BG* in order to grant the bus to the requesting device. The requesting device will then most likely respond with BGACK. The MC68HC000 will not take back the bus until BR and BGACK* are both negated.		If BR* is asserted when the MC68HC000 comes out of reset, it will assert BG* in order to grant the bus to the requesting device. The requesting device will then most likely respond with BGACK. The MC68HC000 will not take back the bus until BR and BGACK* are both negated.
		+
		+	[[Category:68k]]

← Older revision		Revision as of 20:21, 12 April 2011
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−	[~~http://www.elinux.org/~~Flameman#master_index]	+	For more interesting projects done by Flameman, be sure to checkout his [[Flameman#master_index\|project index]]

	EARLY PROOF VERSION OF THIS PAGE		EARLY PROOF VERSION OF THIS PAGE

← Older revision		Revision as of 19:29, 3 December 2009
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		+	[http://www.elinux.org/Flameman#master_index]
		+
	EARLY PROOF VERSION OF THIS PAGE		EARLY PROOF VERSION OF THIS PAGE

← Older revision		Revision as of 10:19, 25 October 2009
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	http://www.toodoc.com/mc68008-ebook.html		http://www.toodoc.com/mc68008-ebook.html
		+
		+
		+	== mc68020 brief ==
		+
		+	Motorola 68020 (MC68020) is a 32-bit microprocessor compatible with earlier members of 680x0 family - 68000, 68008 and 68010. Address bus width on the 68020 is increased to 32 bits, which allows the processor to address up to 4 GB of memory. Data bus width is also increased to 32 bits, though if necessary the 68020 can work with 8- and 16-bit data buses. Other Motorola 68020 enhancements include:
		+
		+	* Execution time of many instructions was reduced.
		+	* To improve CPU performance, a 256-byte instruction cache was added to the CPU.
		+	* The CPU includes new control registers.
		+	* The CPU has new addressing modes: memory indirect addressing modes, scaled index, and larger displacements.
		+	* New instructions were added to 68020 instruction set: bit field instructions, compare instructions, call module and pack/unpack BCD.
		+	* The MC68020 provides hardware support for Motorola 68881 and 68882 Floating-Point Units.
		+	* Accessing mis-aligned word or long-word data no longer results in a system error, though access to misaligned data is not as fast as access to properly aligned data.
		+
		+	Motorola also manufactured MC68EC020 - embedded version of the MC68020 CPU. The 68EC020 had only 24-bit address bus, and could address up to 16 MB of physical memory. The MC68EC020 was housed in different packages than the Motorola 68020 microprocessor.
		+
		+
		+	model:
		+	clock.min:
		+	clock.max:

	== MC68000/008/010 FAQ ==		== MC68000/008/010 FAQ ==

@@ Line 602: / Line 602: @@
 * 1 You can not do hardware single-stepping of the processor.
 * 2 You cannot perform a retry.
-* 3 The processor will reset itself if you get a double bus error (by
+* 3 The processor will reset itself if you get a double bus error (by asserting   HALT*).
 asserting   HALT*).
-−
-−
 === Is it okay to assert the MC68000 VPA* and DTACK* inputs at the same time? ===

@@ Line 584: / Line 584: @@
-Tying HALT* and RESET* together will not cause any problems for the
+Tying HALT* and RESET* together will not cause any problems for the MC68000.As you probably know, RESET* on the MC68000 should never be asserted without asserting HALT* as well. You must realize, however, that tying the two lines together introduces the following three restrictions:
 MC68000.As you probably know, RESET* on the MC68000 should never be
 asserted without asserting HALT* as well. You must realize, however, that
 tying the two lines together introduces the following three restrictions:
 * 1 You can not do hardware single-stepping of the processor.
 * 2 You can not perform a retry.
-* 3 The processor will reset itself if you get a double bus error (by
+* 3 The processor will reset itself if you get a double bus error (by asserting HALT*).
-asserting HALT*).
-−
-Many systems can function within the bounds of the above restrictions and
-operate without problems when HALT* and RESET* are tied together.
 === Should I assert RESET* on the MC68000 without asserting HALT* as well? ===

@@ Line 716: / Line 716: @@
-Interrupt latency is the time from when an interrupt occurs to when the
+Interrupt latency is the time from when an interrupt occurs to when the first instruction of the interrupt handler is started. The amount of time required for this will depend the processor, what the processor is doing when the interrupt occurs, and the speed with which the memory responds to
 first instruction of the interrupt handler is started. The amount of time
 required for this will depend the processor, what the processor is doing
 when the interrupt occurs, and the speed with which the memory responds to
 reads and writes.
-Worst case interrupt latency is the absolute maximum amount of time it will
+Worst case interrupt latency is the absolute maximum amount of time it will take for the processor to respond to the interrupt for a given set of conditions. A given interrupt may respond sooner (and usually will), but it will never take longer. The selection of the conditions can have a major impact on the interrupt latency. For example, the number of wait states on writes will effect the time it takes to stack the interrupt stack frame. An infinite number of wait states on writes would result in an infinite interrupt latency.
 take for the processor to respond to the interrupt for a given set of
 conditions. A given interrupt may respond sooner (and usually will), but it
 will never take longer. The selection of the conditions can have a major
 impact on the interrupt latency. For example, the number of wait states on
 writes will effect the time it takes to stack the interrupt stack frame. An
 infinite number of wait states on writes would result in an infinite
 interrupt latency.
-The following lists the interrupt latency for a given processor and the
+The following lists the interrupt latency for a given processor and the conditions assumed.
 conditions assumed.
 <pre>
@@ Line 756: / Line 745: @@
 clks
 </pre>
 === How many transistors are on each of the MC68000 family devices? ===

@@ Line 797: / Line 797: @@
-If BR* is asserted when the MC68HC000 comes out of reset, it will assert
+If BR* is asserted when the MC68HC000 comes out of reset, it will assert BG* in order to grant the bus to the requesting device. The requesting device will then most likely respond with BGACK*. The MC68HC000 will not take back the bus until BR* and BGACK* are both negated.
 BG* in order to grant the bus to the requesting device. The requesting
 device will then most likely respond with BGACK*. The MC68HC000 will not
 take back the bus until BR* and BGACK* are both negated.

@@ Line 686: / Line 686: @@
-AS* remains inactive during reset. It will take an undetermined amount of
+AS* remains inactive during reset. It will take an undetermined amount of time after reset before AS* will become valid. However, if you are not getting an AS* after you come out of reset, you should check the following signals:
 time after reset before AS* will become valid. However, if you are not
-getting an AS* after you come out of reset, you should check the following
+* 1 Check to make sure BR* and BGACK* are negated to make sure you are not arbitrating the bus away from the MC68000.
 signals:
 * 1 Check to make sure BR* and BGACK* are negated to make sure you are not
 arbitrating the bus away from the MC68000.
 * 2 Check to make sure HALT* is negated.
 === Intel has a pin that allows the signals to tri-state. Does the MC68000 have something similar? ===

@@ Line 654: / Line 654: @@
-* 1 The MC68000 is a 16-bit processor, whereas the MC68008 is an 8-bit
+* 1 The MC68000 is a 16-bit processor, whereas the MC68008 is an 8-bit processor.
-processor.
+* 2 Therefore, UDS* and LDS* on the MC68000 are replaced by DS* and A0 on the MC68008.
-* 2 Therefore, UDS* and LDS* on the MC68000 are replaced by DS* and A0 on
+* 3 The MC68008 uses two-wire bus arbitration, whereas the MC68000 uses three-wire bus arbitration.
-the MC68008.
+* 4 The MC68000 supports three interrupt lines and, therefore, seven interrupt levels. The MC68008 supports only two interrupt lines and, therefore, three interrupt levels. The MC68008 PLCC package supports three interrupt lines like the MC68000.
-* 3 The MC68008 uses two-wire bus arbitration, whereas the MC68000 uses
+* 5 The MC68000 provides 16 Mbytes of addressable space. The MC68008 has 20 address lines creating 1 Mbyte of addressable space. The MC68008 PLCC package has 21 address lines for 2 Mbytes of addressable space.
-three-wire bus arbitration.
+* 6 The MC68008 does not have a VMA* signal as does the MC68000, but this signal can be generated with some simple external logic (see M68000 Users Manual (M68000UM/AD)).
 * 4 The MC68000 supports three interrupt lines and, therefore, seven
 interrupt levels. The MC68008 supports only two interrupt lines and,
 therefore, three interrupt levels. The MC68008 PLCC package supports three
 interrupt lines like the MC68000.
 * 5 The MC68000 provides 16 Mbytes of addressable space. The MC68008 has 20
 address lines creating 1 Mbyte of addressable space. The MC68008 PLCC
 package has 21 address lines for 2 Mbytes of addressable space.
 * 6 The MC68008 does not have a VMA* signal as does the MC68000, but this
 signal can be generated with some simple external logic (see M68000 Users
 Manual (M68000UM/AD)).
 * 7 The MC68000 and MC68008 are not pin compatible.
-It should be noted that the MC68EC000 provides a lower cost solution
+It should be noted that the MC68EC000 provides a lower cost solution compared to the MC68008 and is available at more frequencies than the MC68008. The MC68EC000 can operate in either 8-bit or 16-bit mode and does not include the 6800 peripheral interface, but is virtually identical to the MC68000 in every other way. If you are planning to do a design with the MC68008, it would be worth your time to consider the option of using the MC68EC000 instead.
 compared to the MC68008 and is available at more frequencies than the
 MC68008. The MC68EC000 can operate in either 8-bit or 16-bit mode and does
 not include the 6800 peripheral interface, but is virtually identical to
 the MC68000 in every other way. If you are planning to do a design with the
 MC68008, it would be worth your time to consider the option of using the
 MC68EC000 instead.
-−
-−
 === During a byte access on the MC68000, which bits of the data bus are read/written? ===