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amcc/ibm walnut ppc405gp

walnut - IBM PPC405GP EVB


The board consists of:

  • CPU PowerPC 405GP running at 200Mhz
  • RAM PC133 SDRAM slot, currently, only supports single sidded DIMMs
  • LAN On-chip 405GP ethernet, board doesn't have an ethernet MAC address (the monitor/bootloader is able to fix it)
  • UART 2xDCE serial port, speeds up to 230k, only tested to 115200bps
  • PCI for pci slots, keyed for 5V only cards
  • ROM 512k of boot flash, AMD 29LV040B (amd29lv040b.pdf), socketed
  • POWER the board need ATX power
  • System PCB ATX board size
  • RTC the real time clock chip is???
  • FIRMWARE ibm-evb-mon (horrible)


   A fast, flexible solution for embedded developers.

General Description The AMCC PowerPC 405GP and 405GPr family of 32-bit RISC processors is designed to provide a flexible, fast time-to- market hardware solution to satisfy the demands of high-performance embedded applications. Implemented in the scalable PowerPC architecture, the 405GP and 405GPr processors maintain code compatibility with other PowerPC processors for ease in migration and faster time-to-market. An optimized balance of performance, low power, and features makes them ideal solutions for communication, data storage, and pervasive computing applications.

   The 405GP and 405GPr processors support speeds of up to 266MHz and 400MHz respectively. Both incorporate a rich mix of features, such as a PCI interface, an SDRAM Controller, a 64-bit on-chip CoreConnect bus, Ethernet and other on-chip peripheral support, and the IBM CodePack™ code compression engine. In addition, power management features, a small form factor, and low power consumption make the AMCC 405 processor family an ideal platform for applications ranging from networking to video.
       * High-performance, low-power processors for the most demanding embedded applicationsPowerPC 405GP/405GPr Embedded Processors deliver up to 400MHz performance and a rich mix of features for Internet, communication, data storage, consumer, and imaging applications
       * Includes on-chip SRAM with single-cycle access for faster processing in data-intensive applications, such as routers and switches
       * Supports full application-code compatibility with all other PowerPC® processors for seamless migration
       * Uses the award-winning 64-bit IBM CoreConnect™ high-performance on-chip bus
       * Offers a wide array of small-footprint- package options for high-density applications, such as telecommunications devices
       * Employs the IBM CodePack™ code compression core to reduce system memory requirements and cost
       * On-chip SDRAM Controller
             o Contains separate 32-byte read and 128-byte write buffers
             o Programmable address mapping
       * External Peripheral Controller
             o Supports ROM, EPROM, SRAM
             o Flash and slave peripheral I/O devices
             o 8-, 16-, 32-bit external data bus width
             o Programmable address mapping
       * External Bus Master Controller - Allows external masters to access SDRAM and PCI
       * DMA Controller
             o 4 independent channels
             o Supports transfers between SDRAM, PCI, internal UARTs, and devices on the external peripheral bus
       * PCI Interface
             o 32-bit PCI V2.2 compatible
             o Synchronous and asynchronous operation
             o Internal PCI arbiter supports six PCI masters
             o Supports external arbitration
       * On-chip Ethernet Support
             o 10/100 MAC
             o Dedicated DMA controller
       * CodePack Decompression
             o Stores instructions in memory in compressed format
             o Improves code density by up to 40%
       * Other On-chip Peripherals
             o 2 serial ports
             o Master and slave IIC controller
             o Up to 24 general purpose I/Os
             o Interrupt controller including up to 13 external interrupts

WindRiver VxWorks


     walnut - IBM PPC405GP EVB



     This reference entry provides board-specific information necessary to run
     VxWorks for the walnut (IBM PPC405GP) BSP. Before using a board with
     VxWorks, verify that the board runs in the factory configuration by using
     vendor-supplied ROMs and jumper settings and checking the RS-232
     connection. This BSP supports the PowerPC 405GP Rev D and Rev E parts. Rev
     B and Rev C support is deprecated; support remains as in original release,
     but has not been validated nor upgraded for this release. Rev A parts are
     no longer supported with this release.

  Boot ROMs
     The IBM 405GP Evaluation Board uses a single VxWorks-supplied AMD Am29F040
     ROM (total 512KB). Install the ROM as follows:

     ROM  Socket
     -    U27

     The BSP supports the NVRAM (Dallas Semiconductor DS1743) on the walnut
     board. The boot parameters will be preserved when the system is powered

     Not applicable.


  Supported Features
     The following features are supported in this release:
        - MMU on the PPC405GP processor (MMU_BASIC only).
        - System Timer (uses 405GP PIT hardware timer)
        - Auxiliary Timer (uses 405GP FIT hardware timer)
        - Watchdog Timer (uses 405GP WDT hardware timer)
        - Both 405GP integrated 16550-style serial ports
        - 405GP integrated Universal Interrupt Controller (UIC)
        - MAL/EMAC (integrated Memory Access Layer and 10/100 Ethernet MAC)
        - 405GP PCI controller
        - AMD 79C97x family of Ethernet controller (using ln97xEnd driver)
           - Allied Telesyn 2450T adapter (AMD 79C970) has been tested
           - Allied Telesyn 2700TX adapter (AMD 79C972) has been tested
           - other adapters with the same AMD controller may also work.
        - SDRAM autoconfiguration (the default 32MB SDRAM DIMM can be replaced
     with      up to a 128MB DIMM) using IIC to read the DIMM SEEPROM
        - ECC SDRAM
        - NVRAM (Dallas Semiconductor DS1743)
        - Real-time clock (Dallas Semiconductor DS1743) using ds1643rtc.c driver
        - JTAG RISCWatch bootrom flash programming tool


     This section documents the details of the device drivers and board hardware

     The chip drivers used by this BSP are:
     It also provides DCR access routines for the following functional units:
       - IBM DMA controller
      - IBM external bus controller
      - IBM Memory Access Layer (MAL)
      - IBM SDRAM controller
      - IBM Universal Int Controller (UIC)

  Memory Maps
     This BSP supports MMU on the PPC405GP processor. Memory is mapped using a
     fixed page size of 4K.

     The sysPhysMemDesc[] array in sysLib.c is used to initialize the Page Table
     Entry (PTE) array used by the MMU to translate addresses with single page
     (4k) granularity. Address translations for local RAM, memory mapped PCI
     bus, memory mapped IO space and local PROM/FLASH are set here. PTEs are
     held in a 2-level page table. There is one Level 1 page table and several
     Level 2 page tables. The size of the Level 1 table is 4K and the size of
     each Level 2 page table is 8K. Each Level 2 table can map up to 4MB of
     contiguous memory space.

  Calculating size of page table required
     For the following memory map we can calculate the page table size required
     as follows:

     Memory Area    Address Range Mapped   Size  Number of Level 2 pages
     Local Memory   0 - Ram size           32MB  8
     PCI Memory     0x80000000-0x83FFFFFF  64MB  16
     PCI IO Regn 1  0xE8000000-0xE800FFFF  64K   1
     PCI IO Regn 2  0xE8800000-0xE88FFFFF  1MB   1
     PCI CFG        0xEEC00000-0xEEC00FFF  4K    1
     PCI IACK       0xEED00000-0xEED00FFF  4K    0 *
     PP Bridge      0xEF400000-0xEF400FFF  4K    1
     UART IO Space  0xEF600000-0xEF600FFF  4K    0 *
     NVRAM Space    0xF0000000-0xF0001FFF  8K    1
     Flash          0xFFF80000-0xFFFFFFFF  512K  1

      * included in previous L2 page

      Total # of L2 pages = 30
      Total Memory Required for page table = 30 * 8 + 4 = 244 K.

     By default, to increase performance the instruction MMU (IMMU) is turned
     off. In this case, instruction cacheability is controlled by ICCR (which by
     default is set to cache all RAM). The IMMU can be re-enabled by defining
     USER_I_MMU_ENABLE in config.h.

  Serial Configuration
     The default configuration of the serial ports are 9600bps, 8 data bits, no
     parity, 1 stop bit.

  Network Configuration
     The Enhanced Network Driver (END) used with the integrated EMAC Ethernet
     core is "ibmEmacEnd": Note that the boot device name is now "emac", rather
     than "ibmEmac". The EMAC works at either 10Mbps or 100Mbps. EMAC gets the
     results of the PHY's auto-negotiation process over the MII interface.
     board. This controller uses the ln97xEnd driver provided with VxWorks.

     The Ethernet hardware address is configurable at run-time. The first three
     bytes of the address are always assumed to be 0x0004AC (IBM) and the last
     three bytes are configurable and stored in NVRAM at address 0xF0000500. To
     make the ethernet hardware address match the address printed on the decal
     attached to the Walnut board use the following example as a guide.

     Ethernet hardware address on the Walnut board decal: 0004AC3E4B22
      - boot VxWorks
      - execute the following command from the shell:

              sysLanIbmEmacEnetAddrSet 0x00, 0x04, 0xAC, 0x3E, 0x4B, 0x22

  Supported BootRom builds
     The following bootrom file types are supported in this release. When using
     a Rev B or Rev C processor (which are deprecated), the patch405b.exe or
     patch405c.exe tool must be run on the entire ELF file. If a compressed
     bootrom is built, this is not possible.

     bootrom_uncmp      (405GP Rev B (deprecated), C (deprecated), D, E)
     bootrom_uncmp.hex  (405GP Rev B (deprecated), C (deprecated), or D, E)
     bootrom            (405GP Rev D, E only)
     bootrom.hex        (405GP Rev D, E only)

     ** Note: bootrom builds are only supported through the command line
     makefiles -- do not use the project mechanism to build a boot ROM.

     For PPC405GP_REVB (deprecated):

     A batch file has been provided that will post-process the bootrom_uncmp
     file. After bootrom_uncmp is built, run the bootrrb.bat file. bootrrb.bat
     will modify bootrom_uncmp and will create a new bootrom_uncmp.hex.

     For PPC405GP_REVC (deprecated):

     A batch file has been provided that will post-process the bootrom_uncmp
     file. After bootrom_uncmp is built, run the bootrrc.bat file. bootrrc.bat
     will modify bootrom_uncmp and will create a new bootrom_uncmp.hex.

     For PPC405GP_REVD_OR_E:

     It is not necessary to post-process the bootrom files when using the 405GP
     Rev D or E processor.

     For all processor revisions:

     The standard uncompressed ROM and ROM-resident project configuration are
     not supplied because they will not fit in the bootrom.

  Creating a bootrom, and bringing up vxWorks
     Create a bootrom by either

      a) Rebuilding bootrom_uncmp.hex image and programming it into an
      AMD 29F040 flash part using the following steps:

      - For PPC405GP_REVD_OR_E
              - make bootrom_uncmp.hex or bootrom.hex

      b) If you have a JTAG RISCWatch processor probe, you can use
         vx_rw_flash.cmd to program the flash part (see below).

     Connect a terminal or terminal emulator to the board (the 9 pin connector
     closest to the printed circuit board). Emulator parameters should be set to
     9600bps, 8 data bits, no parity, 1 stop bit. Power-up the board, you should
     get an error because the default boot line in config.h is not 100% correct
     for your environment. Type in new configuration parameters using the
     bootrom menu (set boot device : emac). Your new configuration will be
     stored in the NVRAM.

  Workbench bootrom flash programming utility
      a) Install the WindRiver ICE and power it on.

      Connect the JTAG interface cable from the Wind River ICE to the
      PPC405GP board JTAG connector (J24 located on the CPU card). When all
      of the connections have been made, power up the target board and
      create a Wind River ICE connection in Workbench.

      b) Configure the Workbench connection.

      When creating the connection, specify the PPC405GP CPU.
      Enter the IP address of the Wind River ICE when requested.

      c) Load the proper PPC405GP register setting for WindRiver ICE.

      Once you have connected the probe to the CPU, right-click on the
      connection in the target manager and attach to the CPU core. At
      this point, you can go to the main Workbench Window tab at the top
      of the view and select "show view". Browse the view list and select
      OCD Command Shell. This launches the original BKM command shell.
      Navigate to the target manager and right-click on core(405GP). Select
      the reset tab. You can now put the register file provided by
             the installation in "play register file" (for example, 
             registers/PowerPC/4xx/IBM/405gp.reg). Reset with IN then click the 
             reset download button. You have now loaded the target board with 
             enough settings to program the boot ROM. Close the Reset and 
             Download window after the register file playback finishes.
             Select "Window > show view" again and select Flash Programmer.

      d) Converting the bootrom.hex file to bootrom.bin.

      Select the Add/Remove tab in the flash programmer. Click
      "convert file" and navigate to the boot loader project you created
      previously e.g. WindRiver\workspace\PPC405BootProj\bootrom.hex.
      Select the project. The start address should be 0x0 and the end
      address should be set to 0xffffffff. Click "convert and add" to convert
      the file.
              At this point, the file is added to the list. Click on the start
      address entry (should be 0x0) and change it to 0xfff80000. The file
      is now ready for programming.

      e) Program the PPC405GP flash.


      Go to OCD command shell and type IN. Be sure this returns the BKM

  RISCWatch bootrom flash programming utility
     An IBM RISCWatch based command file (vx_rw_flash.cmd) is provided that will
     program bootrom_uncmp.hex into the AMD Am29F040 flash part on the Walnut
     board. A RISCWatch JTAG processor probe and RISCWatch software version 4.5
     or newer is required to use this utility.


     The vx_rw_flash.cmd utility may need modification if you use a different
     SDRAM DIMM than was shipped with the Walnut board (see notes inside

     To use this utility,
       - make bootrom_uncmp via the command line interface (not with the IDE).
       - Run the bootrr_.bat batch file for the correct processor revision.
      This step will create a patched version of bootrom_uncmp.hex
      NOTE: The manual step of adding the branch instruction to
      bootrom_uncmp.hex is NOT necessary if using this utility!
       - Start IBM JTAG RISCWatch
       - Make sure that the RISCWatch search path is set up to find files
      in the Walnut BSP directory. One way to do this is to execute the
      following RISCWatch command:
         srchpath add c:\WR\VxWorks\target\config\walnut
       - Execute the following command to start the flash programming process.
      This example will place the bootrom_uncmp.hex file into the flash.
         exec vx_rw_flash.cmd {"bootrom_uncmp.hex"}


  PowerPC 405GP Rev A (PVR = 0x40110000)
     This initial hardware sample is no longer supported.

  PowerPC 405GP Rev B (PVR = 0x40110040) errata
     There are errata in the 405GP Rev B chip that affect the operation of this
     Board Support Package. You should familiarize yourself with them. A current
     405GP errata list is available from the PowerPC Technical support group
     (ppcsupp@us.ibm.com). To avoid 405GP Rev B errata a tool patch405b.exe has
     been included. This tool searches an ELF executable file (output of the
     linker) for certain patterns of instructions related to the above errata.
     If it finds a potential problem, it uses reserved space provided by
     patchtblb.s to create a "patch" which will avoid the errata. The patch
     table is allocated inside of sysALib.s because it includes patchtblb.s.

     If you are using a 405GP Rev B be sure to define PPC405GP_REVB in config.h.

  PowerPC 405GP Rev C (PVR = 0x40110082) errata
     There are errata in the 405GP Rev C chip that affect the operation of this
     Board Support Package. You should familiarize yourself with them. A current
     405GP errata list is available from the PowerPC Technical support group
     (ppcsupp@us.ibm.com). To avoid 405GP Rev C errata a tool patch405c.exe has
     been included. This tool searches an ELF executable file (output of the
     linker) for certain patterns of instructions related to the above errata.
     If it finds a potential problem, it uses reserved space provided by
     patchtblc.s to create a "patch" which will avoid the errata. The patch
     If you are using a 405GP Rev D be sure to define PPC405GP_REVD_OR_E in

  PowerPC 405GP Rev E (PVR = 0x40110145) errata
     There are errata in the 405GP Rev E chip that affect the operation of this
     Board Support Package. You should familiarize yourself with them. A current
     405GP errata list is available from the PowerPC Technical support group

     If you are using a 405GP Rev E be sure to define PPC405GP_REVD_OR_E in

  PowerPC 405GPr Rev B (PVR = 0x50910951) errata
     There are errata in the 405GPr Rev B chip that affect the operation of this
     Board Support Package. You should familiarize yourself with them. A current
     405GPr errata list is available from the PowerPC Technical support group

     If you are using a 405GPr Rev B be sure to define PPC405GPR_REVB in


     Please refer to the following documents for further information on the
     Walnut board.

     PowerPC 405 Reference Board Manual located at
     405GP_GPR/PPC405GP_EBM2006__v1_00.pdf obtained from http://www.amcc.com
     (also on the PowerPC Embedded Processors, Cores, and Tools CDROM)

     405GP_settings.pdf included in this BSP.


     VxWorks Programmer's Guide: Configuration, VxWorks Programmer's Guide:
     Architecture Appendix

boot format

original firmware

netbsd-guide says "Do not use the plain ELF kernel as the file provided to the firmware, use the ``netbsd.img file (which is in the format the firmware expects). Of course, you should put the matching ``netbsd as /netbsd on your root file system, otherwise some kernel grovellers won't work"

what is the binary format expected by the original firmware ?


ibm/amcc-walnut jtag connector

(01) TDO (02) nc
(03) TDI (04) nc
(05) nc (06) 3.3v
(07) TCK (08) nc
(09) TMS (10) nc
(11) HALT (12) nc
(13) nc (14) *NC*
(15) nc (16) gnd

dht-walnut jtag pinout


  • DHT-Walnut: JTAG Pin Out Connector Specifications for DHT-walnut-PPC405GP
  • AMCC-PPC4xx: JTAG Pin Out Connector Specifications for AMCC PPC 44X, 40X (4XX) Processors: 405EP, 405GP, 405GPR, 440GP, 440EP, 440GX, 440GR, 440EPX, 440GRX, 440SP, 440SPE

02 nc nc
05 *NC*<--- *NC*<---
06 Vcc Vcc
08 nc KSTP_IN
10 nc nc
12 nc nc
14 nc reserved
16 gnd gnd

Pin Out description

  • TDO=JTAG Test Data Out
  • TDI=JTAG Test Data In
  • TRST=JTAG Test Reset
  • TCK=JTAG Test Clock
  • TMS=JTAG Test Mode Select
  • *NC*=not connected, used as cable reference
  • nc=simply not connected
  • SRESET=Soft-Reset
  • HRESET=Hard-Reset
  • KSTP_OUT=?
  • CKSTP_IN=?
  • Vcc=board ref voltage, 3V

firmware replacing

see dht-walnut "recover from a breakage" ... using that procedure you will be able to replace the ibm/amcc-walnut original firmware with uboot