Difference between revisions of "JTAG"

From eLinux.org
Jump to: navigation, search
(Tools)
(Tutorial)
Line 9: Line 9:
 
=== Tutorial ===
 
=== Tutorial ===
 
[[Media:boundryscan_tutorial.pdf|Tutorial from Asset Intertech]]
 
[[Media:boundryscan_tutorial.pdf|Tutorial from Asset Intertech]]
 +
 +
[http://tree.celinuxforum.org/CelfPubWiki/ELC2009Presentations?action=AttachFile&do=get&target=DebuggingWithJtagCelf2009.pdf Embedded Linux JTAG debugging]
  
 
=== Hardware (emulators) ===
 
=== Hardware (emulators) ===

Revision as of 16:12, 6 July 2009

Joint Test Action Group, referring to IEEE Standard 1149.1: Four-pin (plus power/ground) interface designed to test connections between chips. Interface is serial (clocked via the TCK pin). Configuration is performed by manipulating a state machine one bit at a time (via TMS pin), then transferring one bit of data in and out per TCK clock (via TDI and TDO pins, respectively). Different instruction modes can be loaded to read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips). Operating frequency varies per chip, but is typically 10-100MHz TCK (10-100ns per bit time). The description of how JTAG is implemented for a specific device is described in a file specific to that device called a BSDL file.

Information

Tutorial

Tutorial from Asset Intertech

Embedded Linux JTAG debugging

Hardware (emulators)

Tools