JuiceBox Code Lcd Cpu Header
(file: s3c44b0x.h)
#ifndef __S3C44B0X_H #define __S3C44B0X_H /* CPU register definitions for the Samsung S3C44B0X Assumes little endian mode, with all but the UART TX/RX holding registers as 32 bit words. The RTC regs are probably supposed to be 8 bit, but they seem to work as 32. Read-only registers are not defined as such. */ /****** CPU WRAPPER */ #define syscfg ((uint32_t volatile* const) 0x01c00000) /* SYSCFG (System Configuration) */ #define ncachbe0 ((uint32_t volatile* const) 0x01c00004) /* NCACHBE0 (Non Cacheable Area 0) */ #define ncachbe1 ((uint32_t volatile* const) 0x01c00008) /* NCACHBE1 (Non Cacheable Area 1) */ #define sbuscon ((uint32_t volatile* const) 0x01c40000) /* SBUSCON (System Bus Control) */ /****** MEMORY CONTROLLER */ #define bwscon ((uint32_t volatile* const) 0x01c80000) /* BWSCON (Bus Width & Wait Status Control) */ #define bankcon0 ((uint32_t volatile* const) 0x01c80004) /* BANKCON0 (Boot ROM Control) */ #define bankcon1 ((uint32_t volatile* const) 0x01c80008) /* BANKCON1 (BANK1 Control) */ #define bankcon2 ((uint32_t volatile* const) 0x01c8000c) /* BANKCON2 (BANK2 Control) */ #define bankcon3 ((uint32_t volatile* const) 0x01c80010) /* BANKCON3 (BANK3 Control) */ #define bankcon4 ((uint32_t volatile* const) 0x01c80014) /* BANKCON4 (BANK4 Control) */ #define bankcon5 ((uint32_t volatile* const) 0x01c80018) /* BANKCON5 (BANK5 Control) */ #define bankcon6 ((uint32_t volatile* const) 0x01c8001c) /* BANKCON6 (BANK6 Control) */ #define bankcon7 ((uint32_t volatile* const) 0x01c80020) /* BANKCON7 (BANK7 Control) */ #define refresh ((uint32_t volatile* const) 0x01c80024) /* REFRESH (DRAM/SDRAM Refresh Control) */ #define banksize ((uint32_t volatile* const) 0x01c80028) /* BANKSIZE (Flexible Bank Size) */ #define mrsrb6 ((uint32_t volatile* const) 0x01c8002c) /* MRSRB6 (Mode register set for SDRAM) */ #define mrsrb7 ((uint32_t volatile* const) 0x01c80030) /* MRSRB7 (Mode register set for SDRAM) */ /****** UART */ #define ulcon0 ((uint32_t volatile* const) 0x01d00000) /* ULCON0 (UART 0 Line Control) */ #define ulcon1 ((uint32_t volatile* const) 0x01d04000) /* ULCON1 (UART 1 Line Control) */ #define ucon0 ((uint32_t volatile* const) 0x01d00004) /* UCON0 (UART 0 Control) */ #define ucon1 ((uint32_t volatile* const) 0x01d04004) /* UCON1 (UART 1 Control) */ #define ufcon0 ((uint32_t volatile* const) 0x01d00008) /* UFCON0 (UART 0 FIFO Control) */ #define ufcon1 ((uint32_t volatile* const) 0x01d04008) /* UFCON1 (UART 1 FIFO Control) */ #define umcon0 ((uint32_t volatile* const) 0x01d0000c) /* UMCON0 (UART 0 Modem Control) */ #define umcon1 ((uint32_t volatile* const) 0x01d0400c) /* UMCON1 (UART 1 Modem Control) */ #define utrstat0 ((uint32_t volatile* const) 0x01d00010) /* UTRSTAT0 (UART 0 Tx/Rx Status) */ #define utrstat1 ((uint32_t volatile* const) 0x01d04010) /* UTRSTAT1 (UART 1 Tx/Rx Status) */ #define uerstat0 ((uint32_t volatile* const) 0x01d00014) /* UERSTAT0 (UART 0 Rx Error Status) */ #define uerstat1 ((uint32_t volatile* const) 0x01d04014) /* UERSTAT1 (UART 1 Rx Error Status) */ #define ufstat0 ((uint32_t volatile* const) 0x01d00018) /* UFSTAT0 (UART 0 FIFO Status) */ #define ufstat1 ((uint32_t volatile* const) 0x01d04018) /* UFSTAT1 (UART 1 FIFO Status) */ #define umstat0 ((uint32_t volatile* const) 0x01d0001c) /* UMSTAT0 (UART 0 Modem Status) */ #define umstat1 ((uint32_t volatile* const) 0x01d0401c) /* UMSTAT1 (UART 1 Modem Status) */ #define utxh0 ((uint8_t volatile* const) 0x01d00020) /* UTXH0 (UART 0 Transmission Hold) */ #define utxh1 ((uint8_t volatile* const) 0x01d04020) /* UTXH1 (UART 1 Transmission Hold) */ #define urxh0 ((uint8_t volatile* const) 0x01d00024) /* URXH0 (UART 0 Receive Buffer) */ #define urxh1 ((uint8_t volatile* const) 0x01d04024) /* URXH1 (UART 1 Receive Buffer) */ #define ubrdiv0 ((uint32_t volatile* const) 0x01d00028) /* UBRDIV0 (UART 0 Baud Rate Divisor) */ #define ubrdiv1 ((uint32_t volatile* const) 0x01d04028) /* UBRDIV1 (UART 1 Baud Rate Divisor) */ /****** SIO */ #define siocon ((uint32_t volatile* const) 0x01d14000) /* SIOCON (SIO Control) */ #define siodat ((uint32_t volatile* const) 0x01d14004) /* SIODAT (SIO Data) */ #define sbrdr ((uint32_t volatile* const) 0x01d14008) /* SBRDR (SIO Baud Rate Prescaler) */ #define itvcnt ((uint32_t volatile* const) 0x01d1400c) /* ITVCNT (SIO Interval Counter) */ #define dcntz ((uint32_t volatile* const) 0x01d14010) /* DCNTZ (SIO DMA Count Zero) */ /****** IIS */ #define iiscon ((uint32_t volatile* const) 0x01d18000) /* IISCON (IIS Control) */ #define iismod ((uint32_t volatile* const) 0x01d18004) /* IISMOD (IIS Mode) */ #define iispsr ((uint32_t volatile* const) 0x01d18008) /* IISPSR (IIS Prescaler) */ #define iisfifcon ((uint32_t volatile* const) 0x01d1800c) /* IISFIFCON (IIS FIFO Control) */ #define iisfif ((uint32_t volatile* const) 0x01d18010) /* IISFIF (IIS FIFO Entry) */ /****** I/O PORT */ #define pcona ((uint32_t volatile* const) 0x01d20000) /* PCONA (Port A Control) */ #define pdata ((uint32_t volatile* const) 0x01d20004) /* PDATA (Port A Data) */ #define pconb ((uint32_t volatile* const) 0x01d20008) /* PCONB (Port B Control) */ #define pdatb ((uint32_t volatile* const) 0x01d2000c) /* PDATB (Port B Data) */ #define pconc ((uint32_t volatile* const) 0x01d20010) /* PCONC (Port C Control) */ #define pdatc ((uint32_t volatile* const) 0x01d20014) /* PDATC (Port C Data) */ #define pupc ((uint32_t volatile* const) 0x01d20018) /* PUPC (Pull-up Control C) */ #define pcond ((uint32_t volatile* const) 0x01d2001c) /* PCOND (Port D Control) */ #define pdatd ((uint32_t volatile* const) 0x01d20020) /* PDATD (Port D Data) */ #define pupd ((uint32_t volatile* const) 0x01d20024) /* PUPD (Pull-up Control D) */ #define pcone ((uint32_t volatile* const) 0x01d20028) /* PCONE (Port E Control) */ #define pdate ((uint32_t volatile* const) 0x01d2002c) /* PDATE (Port E Data) */ #define pupe ((uint32_t volatile* const) 0x01d20030) /* PUPE (Pull-up Control E) */ #define pconf ((uint32_t volatile* const) 0x01d20034) /* PCONF (Port F Control) */ #define pdatf ((uint32_t volatile* const) 0x01d20038) /* PDATF (Port F Data) */ #define pupf ((uint32_t volatile* const) 0x01d2003c) /* PUPF (Pull-up Control F) */ #define pcong ((uint32_t volatile* const) 0x01d20040) /* PCONG (Port G Control) */ #define pdatg ((uint32_t volatile* const) 0x01d20044) /* PDATG (Port G Data) */ #define pupg ((uint32_t volatile* const) 0x01d20048) /* PUPG (Pull-up Control G) */ #define spucr ((uint32_t volatile* const) 0x01d2004c) /* SPUCR (Special Pull-up) */ #define extint ((uint32_t volatile* const) 0x01d20050) /* EXTINT (External Interrupt Control) */ #define extinpnd ((uint32_t volatile* const) 0x01d20054) /* EXTINPND (External Interrupt Pending) */ /****** WATCHDOG TIMER */ #define wtcon ((uint32_t volatile* const) 0x01d30000) /* WTCON (Watchdog Timer Mode) */ #define wtdat ((uint32_t volatile* const) 0x01d30004) /* WTDAT (Watchdog Timer Data) */ #define wtcnt ((uint32_t volatile* const) 0x01d30008) /* WTCNT (Watchdog Timer Count) */ /****** A/D CONVERTER */ #define adccon ((uint32_t volatile* const) 0x01d40000) /* ADCCON (ADC Control) */ #define adcpsr ((uint32_t volatile* const) 0x01d40004) /* ADCPSR (ADC Prescaler) */ #define adcdat ((uint32_t volatile* const) 0x01d40008) /* ADCDAT (Digitized 10 bit Data) */ /****** PWM TIMER */ #define tcfg0 ((uint32_t volatile* const) 0x01d50000) /* TCFG0 (Timer Configuration) */ #define tcfg1 ((uint32_t volatile* const) 0x01d50004) /* TCFG1 (Timer Configuration) */ #define tcon ((uint32_t volatile* const) 0x01d50008) /* TCON (Timer Control) */ #define tcntb0 ((uint32_t volatile* const) 0x01d5000c) /* TCNTB0 (Timer Count Buffer 0) */ #define tcmpb0 ((uint32_t volatile* const) 0x01d50010) /* TCMPB0 (Timer Compare Buffer 0) */ #define tcnto0 ((uint32_t volatile* const) 0x01d50014) /* TCNTO0 (Timer Count Observation 0) */ #define tcntb1 ((uint32_t volatile* const) 0x01d50018) /* TCNTB1 (Timer Count Buffer 1) */ #define tcmpb1 ((uint32_t volatile* const) 0x01d5001c) /* TCMPB1 (Timer Compare Buffer 1) */ #define tcnto1 ((uint32_t volatile* const) 0x01d50020) /* TCNTO1 (Timer Count Observation 1) */ #define tcntb2 ((uint32_t volatile* const) 0x01d50024) /* TCNTB2 (Timer Count Buffer 2) */ #define tcmpb2 ((uint32_t volatile* const) 0x01d50028) /* TCMPB2 (Timer Compare Buffer 2) */ #define tcnto2 ((uint32_t volatile* const) 0x01d5002c) /* TCNTO2 (Timer Count Observation 2) */ #define tcntb3 ((uint32_t volatile* const) 0x01d50030) /* TCNTB3 (Timer Count Buffer 3) */ #define tcmpb3 ((uint32_t volatile* const) 0x01d50034) /* TCMPB3 (Timer Compare Buffer 3) */ #define tcnto3 ((uint32_t volatile* const) 0x01d50038) /* TCNTO3 (Timer Count Observation 3) */ #define tcntb4 ((uint32_t volatile* const) 0x01d5003c) /* TCNTB4 (Timer Count Buffer 4) */ #define tcmpb4 ((uint32_t volatile* const) 0x01d50040) /* TCMPB4 (Timer Compare Buffer 4) */ #define tcnto4 ((uint32_t volatile* const) 0x01d50044) /* TCNTO4 (Timer Count Observation 4) */ #define tcntb5 ((uint32_t volatile* const) 0x01d50048) /* TCNTB5 (Timer Count Buffer 5) */ #define tcnto5 ((uint32_t volatile* const) 0x01d5004c) /* TCNTO5 (Timer Count Observation 5) */ /****** IIC */ #define iiccon ((uint32_t volatile* const) 0x01d60000) /* IICCON (IIC Control) */ #define iicstat ((uint32_t volatile* const) 0x01d60004) /* IICSTAT (IIC Status) */ #define iicadd ((uint32_t volatile* const) 0x01d60008) /* IICADD (IIC Address) */ #define iicds ((uint32_t volatile* const) 0x01d6000c) /* IICDS (IIC Data Shift) */ /****** RTC */ /* The book shows these as 8 bit registers, not 32. Double-check? */ #define rtccon ((uint32_t volatile* const) 0x01d70040) /* RTCCON (RTC Control) */ #define rtcalm ((uint32_t volatile* const) 0x01d70050) /* RTCALM (RTC Alarm) */ #define almsec ((uint32_t volatile* const) 0x01d70054) /* ALMSEC (Alarm Second) */ #define almmin ((uint32_t volatile* const) 0x01d70058) /* ALMMIN (Alarm Minute) */ #define almhour ((uint32_t volatile* const) 0x01d7005c) /* ALMHOUR (Alarm Hour) */ #define almday ((uint32_t volatile* const) 0x01d70060) /* ALMDAY (Alarm Day) */ #define almmon ((uint32_t volatile* const) 0x01d70064) /* ALMMON (Alarm Month) */ #define almyear ((uint32_t volatile* const) 0x01d70068) /* ALMYEAR (Alarm Year) */ #define rtcrst ((uint32_t volatile* const) 0x01d7006c) /* RTCRST (RTC Round Reset) */ #define bcdsec ((uint32_t volatile* const) 0x01d70070) /* BCDSEC (BCD Second) */ #define bcdmin ((uint32_t volatile* const) 0x01d70074) /* BCDMIN (BCD Minute) */ #define bcdhour ((uint32_t volatile* const) 0x01d70078) /* BCDHOUR (BCD Hour) */ #define bcdday ((uint32_t volatile* const) 0x01d7007c) /* BCDDAY (BCD Day) */ #define bcddate ((uint32_t volatile* const) 0x01d70080) /* BCDDATE (BCD Date) */ #define bcdmon ((uint32_t volatile* const) 0x01d70084) /* BCDMON (BCD Month) */ #define bcdyear ((uint32_t volatile* const) 0x01d70088) /* BCDYEAR (BCD Year) */ #define ticint ((uint32_t volatile* const) 0x01D7008C) /* TICINT (Tick time count) */ /****** CLOCK & POWER MANAGEMENT */ #define pllcon ((uint32_t volatile* const) 0x01d80000) /* PLLCON (PLL Control) */ #define clkcon ((uint32_t volatile* const) 0x01d80004) /* CLKCON (Clock Control) */ #define clkslow ((uint32_t volatile* const) 0x01d80008) /* CLKSLOW (Slow clock Control) */ #define locktime ((uint32_t volatile* const) 0x01d8000c) /* LOCKTIME (PLL lock time Counter) */ /****** INTERRUPT CONTROLLER */ #define intcon ((uint32_t volatile* const) 0x01e00000) /* INTCON (Interrupt Control) */ #define intpnd ((uint32_t volatile* const) 0x01e00004) /* INTPND (Interrupt Request Status) */ #define intmod ((uint32_t volatile* const) 0x01e00008) /* INTMOD (Interrupt Mode Control) */ #define intmsk ((uint32_t volatile* const) 0x01e0000c) /* INTMSK (Interrupt Mask Control) */ #define i_pslv ((uint32_t volatile* const) 0x01e00010) /* I_PSLV (IRQ Interrupt Previous Slave) */ #define i_pmst ((uint32_t volatile* const) 0x01e00014) /* I_PMST (IRQ Interrupt Priority Master) */ #define i_cslv ((uint32_t volatile* const) 0x01e00018) /* I_CSLV (IRQ Interrupt Current Slave) */ #define i_cmst ((uint32_t volatile* const) 0x01e0001c) /* I_CMST (IRQ Interrupt Current Master) */ #define i_ispr ((uint32_t volatile* const) 0x01e00020) /* I_ISPR (IRQ Interrupt Pending Status) */ #define i_ispc ((uint32_t volatile* const) 0x01e00024) /* I_ISPC (IRQ Interrupt Pending Clear) */ #define f_ispr ((uint32_t volatile* const) 0x01e00038) /* F_ISPR (FIQ Interrupt Pending) */ #define f_ispc ((uint32_t volatile* const) 0x01e0003c) /* F_ISPC (FIQ Interrupt Pending Clear) */ /****** LCD CONTROLLER */ #define lcdcon1 ((uint32_t volatile* const) 0x01f00000) /* LCDCON1 (LCD Control 1) */ #define lcdcon2 ((uint32_t volatile* const) 0x01f00004) /* LCDCON2 (LCD Control 2) */ #define lcdcon3 ((uint32_t volatile* const) 0x01f00040) /* LCDCON3 (LCD Control 3) */ #define lcdsaddr1 ((uint32_t volatile* const) 0x01f00008) /* LCDSADDR1 (Frame Upper Buffer Start Address 1) */ #define lcdsaddr2 ((uint32_t volatile* const) 0x01f0000c) /* LCDSADDR2 (Frame Lower Buffer Start Address 2) */ #define lcdsaddr3 ((uint32_t volatile* const) 0x01f00010) /* LCDSADDR3 (Virtual Screen Address) */ #define redlut ((uint32_t volatile* const) 0x01f00014) /* REDLUT (RED Lookup Table) */ #define greenlut ((uint32_t volatile* const) 0x01f00018) /* GREENLUT (GREEN Lookup Table) */ #define bluelut ((uint32_t volatile* const) 0x01f0001c) /* BLUELUT (BLUE Lookup Table) */ #define dp1_2 ((uint32_t volatile* const) 0x01f00020) /* DP1_2 (Dithering Pattern duty 1/2) */ #define dp4_7 ((uint32_t volatile* const) 0x01f00024) /* DP4_7 (Dithering Pattern duty 4/7) */ #define dp3_5 ((uint32_t volatile* const) 0x01f00028) /* DP3_5 (Dithering Pattern duty 3/5) */ #define dp2_3 ((uint32_t volatile* const) 0x01f0002c) /* DP2_3 (Dithering Pattern duty 2/3) */ #define dp5_7 ((uint32_t volatile* const) 0x01f00030) /* DP5_7 (Dithering Pattern duty 5/7) */ #define dp3_4 ((uint32_t volatile* const) 0x01f00034) /* DP3_4 (Dithering Pattern duty 3/4) */ #define dp4_5 ((uint32_t volatile* const) 0x01f00038) /* DP4_5 (Dithering Pattern duty 4/5) */ #define dp6_7 ((uint32_t volatile* const) 0x01f0003c) /* DP6_7 (Dithering Pattern duty 6/7) */ #define dithmode ((uint32_t volatile* const) 0x01f00044) /* DITHMODE (Dithering Mode) */ /****** DMA */ #define zdcon0 ((uint32_t volatile* const) 0x01e80000) /* ZDCON0 (ZDMA0 Control) */ #define zdisrc0 ((uint32_t volatile* const) 0x01e80004) /* ZDISRC0 (ZDMA 0 Initial Source Address) */ #define zdides0 ((uint32_t volatile* const) 0x01e80008) /* ZDIDES0 (ZDMA 0 Initial Destination Address) */ #define zdicnt0 ((uint32_t volatile* const) 0x01e8000c) /* ZDICNT0 (ZDMA 0 Initial Transfer Count) */ #define zdcsrc0 ((uint32_t volatile* const) 0x01e80010) /* ZDCSRC0 (ZDMA 0 Current Source Address) */ #define zdcdes0 ((uint32_t volatile* const) 0x01e80014) /* ZDCDES0 (ZDMA 0 Current Destination Address) */ #define zdccnt0 ((uint32_t volatile* const) 0x01e80018) /* ZDCCNT0 (ZDMA 0 Current Transfer Count) */ #define zdcon1 ((uint32_t volatile* const) 0x01e80020) /* ZDCON1 (ZDMA 1 Control) */ #define zdisrc1 ((uint32_t volatile* const) 0x01e80024) /* ZDISRC1 (ZDMA 1 Initial Source Address) */ #define zdides1 ((uint32_t volatile* const) 0x01e80028) /* ZDIDES1 (ZDMA 1 Initial Destination Address) */ #define zdicnt1 ((uint32_t volatile* const) 0x01e8002c) /* ZDICNT1 (ZDMA 1 Initial Transfer Count) */ #define zdcsrc1 ((uint32_t volatile* const) 0x01e80030) /* ZDCSRC1 (ZDMA 1 Current Source Address) */ #define zdcdes1 ((uint32_t volatile* const) 0x01e80034) /* ZDCDES1 (ZDMA 1 Current Destination Address) */ #define zdccnt1 ((uint32_t volatile* const) 0x01e80038) /* ZDCCNT1 (ZDMA 1 Current Transfer Count) */ #define bdcon0 ((uint32_t volatile* const) 0x01f80000) /* BDCON0 (BDMA 0 Control) */ #define bdisrc0 ((uint32_t volatile* const) 0x01f80004) /* BDISRC0 (BDMA 0 Initial Source Address) */ #define bdides0 ((uint32_t volatile* const) 0x01f80008) /* BDIDES0 (BDMA 0 Initial Destination Address) */ #define bdicnt0 ((uint32_t volatile* const) 0x01f8000c) /* BDICNT0 (BDMA 0 Initial Transfer Count) */ #define bdcsrc0 ((uint32_t volatile* const) 0x01f80010) /* BDCSRC0 (BDMA 0 Current Source Address) */ #define bdcdes0 ((uint32_t volatile* const) 0x01f80014) /* BDCDES0 (BDMA 0 Current Destination Address) */ #define bdccnt0 ((uint32_t volatile* const) 0x01f80018) /* BDCCNT0 (BDMA 0 Current Transfer Count) */ #define bdcon1 ((uint32_t volatile* const) 0x01f80020) /* BDCON1 (BDMA 1 Control) */ #define bdisrc1 ((uint32_t volatile* const) 0x01f80024) /* BDISRC1 (BDMA 1 Initial Source Address) */ #define bdides1 ((uint32_t volatile* const) 0x01f80028) /* BDIDES1 (BDMA 1 Initial Destination Address) */ #define bdicnt1 ((uint32_t volatile* const) 0x01f8002c) /* BDICNT1 (BDMA 1 Initial Transfer Count) */ #define bdcsrc1 ((uint32_t volatile* const) 0x01f80030) /* BDCSRC1 (BDMA 1 Current Source Address) */ #define bdcdes1 ((uint32_t volatile* const) 0x01f80034) /* BDCDES1 (BDMA 1 Current Destination Address) */ #define bdccnt1 ((uint32_t volatile* const) 0x01f80038) /* BDCCNT1 (BDMA 1 Current Transfer Count) */ #endif