http://elinux.org/index.php?title=JuiceBox_Cpu_Regs&feed=atom&action=history 2013-05-23T04:01:15Z Revision history for this page on the wiki MediaWiki 1.21alpha http://elinux.org/index.php?title=JuiceBox_Cpu_Regs&diff=3769&oldid=prev 2007-07-14T09:01:54Z

<p></p> <table class='diff diff-contentalign-left'> <col class='diff-marker' /> <col class='diff-content' /> <col class='diff-marker' /> <col class='diff-content' /> <tr style='vertical-align: top;'> <td colspan='2' style="background-color: white; color:black;">← Older revision</td> <td colspan='2' style="background-color: white; color:black;">Revision as of 09:01, 14 July 2007</td> </tr><tr><td colspan="2" class="diff-lineno">Line 1:</td> <td colspan="2" class="diff-lineno">Line 1:</td></tr> <tr><td class='diff-marker'>−</td><td style="background: #ffa; color:black; font-size: smaller;"><div><del style="color: red; font-weight: bold; text-decoration: none;"></del></div></td><td colspan="2">&#160;</td></tr> <tr><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"><div>&lt;pre&gt;</div></td><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"><div>&lt;pre&gt;</div></td></tr> <tr><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"><div>/* CPU register definitions for the Samsung S3C44B0X</div></td><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"><div>/* CPU register definitions for the Samsung S3C44B0X</div></td></tr> <tr><td colspan="2" class="diff-lineno">Line 220:</td> <td colspan="2" class="diff-lineno">Line 219:</td></tr> <tr><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"></td><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"></td></tr> <tr><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"><div>&lt;/pre&gt;</div></td><td class='diff-marker'>&#160;</td><td style="background: #eee; color:black; font-size: smaller;"><div>&lt;/pre&gt;</div></td></tr> <tr><td colspan="2">&#160;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;"></ins></div></td></tr> <tr><td colspan="2">&#160;</td><td class='diff-marker'>+</td><td style="background: #cfc; color:black; font-size: smaller;"><div><ins style="color: red; font-weight: bold; text-decoration: none;">[[Category:JuiceBox]]</ins></div></td></tr> <!-- diff cache key elinux:diff:version:1.11a:oldid:2212:newid:3769 --> </table>

Chris http://elinux.org/index.php?title=JuiceBox_Cpu_Regs&diff=2212&oldid=prev 2007-03-07T03:32:25Z

<p>Bot (Edward&#039;s framework)</p> <p><b>New page</b></p><div><br /> &lt;pre&gt;<br /> /* CPU register definitions for the Samsung S3C44B0X<br /> Assumes little endian mode, with all but the UART TX/RX <br /> holding registers as 32 bit words. The RTC regs are probably<br /> supposed to be 8 bit, but they seem to work as 32. <br /> Read-only registers are not defined as such. */<br /> <br /> /****** CPU WRAPPER */<br /> <br /> uint32_t volatile* const syscfg=(uint32_t*)0x01c00000; /* SYSCFG (System Configuration) */<br /> uint32_t volatile* const ncachbe0=(uint32_t*)0x01c00004; /* NCACHBE0 (Non Cacheable Area 0) */<br /> uint32_t volatile* const ncachbe1=(uint32_t*)0x01c00008; /* NCACHBE1 (Non Cacheable Area 1) */<br /> uint32_t volatile* const sbuscon=(uint32_t*)0x01c40000; /* SBUSCON (System Bus Control) */<br /> <br /> /****** MEMORY CONTROLLER */<br /> uint32_t volatile* const bwscon=(uint32_t*)0x01c80000; /* BWSCON (Bus Width &amp; Wait Status Control) */<br /> uint32_t volatile* const bankcon0=(uint32_t*)0x01c80004; /* BANKCON0 (Boot ROM Control) */<br /> uint32_t volatile* const bankcon1=(uint32_t*)0x01c80008; /* BANKCON1 (BANK1 Control) */<br /> uint32_t volatile* const bankcon2=(uint32_t*)0x01c8000c; /* BANKCON2 (BANK2 Control) */<br /> uint32_t volatile* const bankcon3=(uint32_t*)0x01c80010; /* BANKCON3 (BANK3 Control) */<br /> uint32_t volatile* const bankcon4=(uint32_t*)0x01c80014; /* BANKCON4 (BANK4 Control) */<br /> uint32_t volatile* const bankcon5=(uint32_t*)0x01c80018; /* BANKCON5 (BANK5 Control) */<br /> uint32_t volatile* const bankcon6=(uint32_t*)0x01c8001c; /* BANKCON6 (BANK6 Control) */<br /> uint32_t volatile* const bankcon7=(uint32_t*)0x01c80020; /* BANKCON7 (BANK7 Control) */<br /> uint32_t volatile* const refresh=(uint32_t*)0x01c80024; /* REFRESH (DRAM/SDRAM Refresh Control) */<br /> uint32_t volatile* const banksize=(uint32_t*)0x01c80028; /* BANKSIZE (Flexible Bank Size) */<br /> uint32_t volatile* const mrsrb6=(uint32_t*)0x01c8002c; /* MRSRB6 (Mode register set for SDRAM) */<br /> uint32_t volatile* const mrsrb7=(uint32_t*)0x01c80030; /* MRSRB7 (Mode register set for SDRAM) */<br /> <br /> /****** UART */<br /> uint32_t volatile* const ulcon0=(uint32_t*)0x01d00000; /* ULCON0 (UART 0 Line Control) */<br /> uint32_t volatile* const ulcon1=(uint32_t*)0x01d04000; /* ULCON1 (UART 1 Line Control) */<br /> uint32_t volatile* const ucon0=(uint32_t*)0x01d00004; /* UCON0 (UART 0 Control) */<br /> uint32_t volatile* const ucon1=(uint32_t*)0x01d04004; /* UCON1 (UART 1 Control) */<br /> uint32_t volatile* const ufcon0=(uint32_t*)0x01d00008; /* UFCON0 (UART 0 FIFO Control) */<br /> uint32_t volatile* const ufcon1=(uint32_t*)0x01d04008; /* UFCON1 (UART 1 FIFO Control) */<br /> uint32_t volatile* const umcon0=(uint32_t*)0x01d0000c; /* UMCON0 (UART 0 Modem Control) */<br /> uint32_t volatile* const umcon1=(uint32_t*)0x01d0400c; /* UMCON1 (UART 1 Modem Control) */<br /> uint32_t volatile* const utrstat0=(uint32_t*)0x01d00010; /* UTRSTAT0 (UART 0 Tx/Rx Status) */<br /> uint32_t volatile* const utrstat1=(uint32_t*)0x01d04010; /* UTRSTAT1 (UART 1 Tx/Rx Status) */<br /> uint32_t volatile* const uerstat0=(uint32_t*)0x01d00014; /* UERSTAT0 (UART 0 Rx Error Status) */<br /> uint32_t volatile* const uerstat1=(uint32_t*)0x01d04014; /* UERSTAT1 (UART 1 Rx Error Status) */<br /> uint32_t volatile* const ufstat0=(uint32_t*)0x01d00018; /* UFSTAT0 (UART 0 FIFO Status) */<br /> uint32_t volatile* const ufstat1=(uint32_t*)0x01d04018; /* UFSTAT1 (UART 1 FIFO Status) */<br /> uint32_t volatile* const umstat0=(uint32_t*)0x01d0001c; /* UMSTAT0 (UART 0 Modem Status) */<br /> uint32_t volatile* const umstat1=(uint32_t*)0x01d0401c; /* UMSTAT1 (UART 1 Modem Status) */<br /> uint8_t volatile* const utxh0=(uint8_t*)0x01d00020; /* UTXH0 (UART 0 Transmission Hold) */<br /> uint8_t volatile* const utxh1=(uint8_t*)0x01d04020; /* UTXH1 (UART 1 Transmission Hold) */<br /> uint8_t volatile* const urxh0=(uint8_t*)0x01d00024; /* URXH0 (UART 0 Receive Buffer) */<br /> uint8_t volatile* const urxh1=(uint8_t*)0x01d04024; /* URXH1 (UART 1 Receive Buffer) */<br /> uint32_t volatile* const ubrdiv0=(uint32_t*)0x01d00028; /* UBRDIV0 (UART 0 Baud Rate Divisor) */<br /> uint32_t volatile* const ubrdiv1=(uint32_t*)0x01d04028; /* UBRDIV1 (UART 1 Baud Rate Divisor) */<br /> <br /> /****** SIO */<br /> uint32_t volatile* const siocon=(uint32_t*)0x01d14000; /* SIOCON (SIO Control) */<br /> uint32_t volatile* const siodat=(uint32_t*)0x01d14004; /* SIODAT (SIO Data) */<br /> uint32_t volatile* const sbrdr=(uint32_t*)0x01d14008; /* SBRDR (SIO Baud Rate Prescaler) */<br /> uint32_t volatile* const itvcnt=(uint32_t*)0x01d1400c; /* ITVCNT (SIO Interval Counter) */<br /> uint32_t volatile* const dcntz=(uint32_t*)0x01d14010; /* DCNTZ (SIO DMA Count Zero) */<br /> <br /> /****** IIS */<br /> uint32_t volatile* const iiscon=(uint32_t*)0x01d18000; /* IISCON (IIS Control) */<br /> uint32_t volatile* const iismod=(uint32_t*)0x01d18004; /* IISMOD (IIS Mode) */<br /> uint32_t volatile* const iispsr=(uint32_t*)0x01d18008; /* IISPSR (IIS Prescaler) */<br /> uint32_t volatile* const iisfifcon=(uint32_t*)0x01d1800c; /* IISFIFCON (IIS FIFO Control) */<br /> uint32_t volatile* const iisfif=(uint32_t*)0x01d18010; /* IISFIF (IIS FIFO Entry) */<br /> <br /> /****** I/O PORT */<br /> uint32_t volatile* const pcona=(uint32_t*)0x01d20000; /* PCONA (Port A Control) */<br /> uint32_t volatile* const pdata=(uint32_t*)0x01d20004; /* PDATA (Port A Data) */<br /> uint32_t volatile* const pconb=(uint32_t*)0x01d20008; /* PCONB (Port B Control) */<br /> uint32_t volatile* const pdatb=(uint32_t*)0x01d2000c; /* PDATB (Port B Data) */<br /> uint32_t volatile* const pconc=(uint32_t*)0x01d20010; /* PCONC (Port C Control) */<br /> uint32_t volatile* const pdatc=(uint32_t*)0x01d20014; /* PDATC (Port C Data) */<br /> uint32_t volatile* const pupc=(uint32_t*)0x01d20018; /* PUPC (Pull-up Control C) */<br /> uint32_t volatile* const pcond=(uint32_t*)0x01d2001c; /* PCOND (Port D Control) */<br /> uint32_t volatile* const pdatd=(uint32_t*)0x01d20020; /* PDATD (Port D Data) */<br /> uint32_t volatile* const pupd=(uint32_t*)0x01d20024; /* PUPD (Pull-up Control D) */<br /> uint32_t volatile* const pcone=(uint32_t*)0x01d20028; /* PCONE (Port E Control) */<br /> uint32_t volatile* const pdate=(uint32_t*)0x01d2002c; /* PDATE (Port E Data) */<br /> uint32_t volatile* const pupe=(uint32_t*)0x01d20030; /* PUPE (Pull-up Control E) */<br /> uint32_t volatile* const pconf=(uint32_t*)0x01d20034; /* PCONF (Port F Control) */<br /> uint32_t volatile* const pdatf=(uint32_t*)0x01d20038; /* PDATF (Port F Data) */<br /> uint32_t volatile* const pupf=(uint32_t*)0x01d2003c; /* PUPF (Pull-up Control F) */<br /> uint32_t volatile* const pcong=(uint32_t*)0x01d20040; /* PCONG (Port G Control) */<br /> uint32_t volatile* const pdatg=(uint32_t*)0x01d20044; /* PDATG (Port G Data) */<br /> uint32_t volatile* const pupg=(uint32_t*)0x01d20048; /* PUPG (Pull-up Control G) */<br /> uint32_t volatile* const spucr=(uint32_t*)0x01d2004c; /* SPUCR (Special Pull-up) */<br /> uint32_t volatile* const extint=(uint32_t*)0x01d20050; /* EXTINT (External Interrupt Control) */<br /> uint32_t volatile* const extinpnd=(uint32_t*)0x01d20054; /* EXTINPND (External Interrupt Pending) */<br /> <br /> /****** WATCHDOG TIMER */<br /> uint32_t volatile* const wtcon=(uint32_t*)0x01d30000; /* WTCON (Watchdog Timer Mode) */<br /> uint32_t volatile* const wtdat=(uint32_t*)0x01d30004; /* WTDAT (Watchdog Timer Data) */<br /> uint32_t volatile* const wtcnt=(uint32_t*)0x01d30008; /* WTCNT (Watchdog Timer Count) */<br /> <br /> /****** A/D CONVERTER */<br /> uint32_t volatile* const adccon=(uint32_t*)0x01d40000; /* ADCCON (ADC Control) */<br /> uint32_t volatile* const adcpsr=(uint32_t*)0x01d40004; /* ADCPSR (ADC Prescaler) */<br /> uint32_t volatile* const adcdat=(uint32_t*)0x01d40008; /* ADCDAT (Digitized 10 bit Data) */<br /> <br /> /****** PWM TIMER */<br /> uint32_t volatile* const tcfg0=(uint32_t*)0x01d50000; /* TCFG0 (Timer Configuration) */<br /> uint32_t volatile* const tcfg1=(uint32_t*)0x01d50004; /* TCFG1 (Timer Configuration) */<br /> uint32_t volatile* const tcon=(uint32_t*)0x01d50008; /* TCON (Timer Control) */<br /> uint32_t volatile* const tcntb0=(uint32_t*)0x01d5000c; /* TCNTB0 (Timer Count Buffer 0) */<br /> uint32_t volatile* const tcmpb0=(uint32_t*)0x01d50010; /* TCMPB0 (Timer Compare Buffer 0) */<br /> uint32_t volatile* const tcnto0=(uint32_t*)0x01d50014; /* TCNTO0 (Timer Count Observation 0) */<br /> uint32_t volatile* const tcntb1=(uint32_t*)0x01d50018; /* TCNTB1 (Timer Count Buffer 1) */<br /> uint32_t volatile* const tcmpb1=(uint32_t*)0x01d5001c; /* TCMPB1 (Timer Compare Buffer 1) */<br /> uint32_t volatile* const tcnto1=(uint32_t*)0x01d50020; /* TCNTO1 (Timer Count Observation 1) */<br /> uint32_t volatile* const tcntb2=(uint32_t*)0x01d50024; /* TCNTB2 (Timer Count Buffer 2) */<br /> uint32_t volatile* const tcmpb2=(uint32_t*)0x01d50028; /* TCMPB2 (Timer Compare Buffer 2) */<br /> uint32_t volatile* const tcnto2=(uint32_t*)0x01d5002c; /* TCNTO2 (Timer Count Observation 2) */<br /> uint32_t volatile* const tcntb3=(uint32_t*)0x01d50030; /* TCNTB3 (Timer Count Buffer 3) */<br /> uint32_t volatile* const tcmpb3=(uint32_t*)0x01d50034; /* TCMPB3 (Timer Compare Buffer 3) */<br /> uint32_t volatile* const tcnto3=(uint32_t*)0x01d50038; /* TCNTO3 (Timer Count Observation 3) */<br /> uint32_t volatile* const tcntb4=(uint32_t*)0x01d5003c; /* TCNTB4 (Timer Count Buffer 4) */<br /> uint32_t volatile* const tcmpb4=(uint32_t*)0x01d50040; /* TCMPB4 (Timer Compare Buffer 4) */<br /> uint32_t volatile* const tcnto4=(uint32_t*)0x01d50044; /* TCNTO4 (Timer Count Observation 4) */<br /> uint32_t volatile* const tcntb5=(uint32_t*)0x01d50048; /* TCNTB5 (Timer Count Buffer 5) */<br /> uint32_t volatile* const tcnto5=(uint32_t*)0x01d5004c; /* TCNTO5 (Timer Count Observation 5) */<br /> <br /> /****** IIC */<br /> uint32_t volatile* const iiccon=(uint32_t*)0x01d60000; /* IICCON (IIC Control) */<br /> uint32_t volatile* const iicstat=(uint32_t*)0x01d60004; /* IICSTAT (IIC Status) */<br /> uint32_t volatile* const iicadd=(uint32_t*)0x01d60008; /* IICADD (IIC Address) */<br /> uint32_t volatile* const iicds=(uint32_t*)0x01d6000c; /* IICDS (IIC Data Shift) */<br /> <br /> /****** RTC */<br /> /* The book shows these as 8 bit registers, not 32. Double-check? */<br /> uint32_t volatile* const rtccon=(uint32_t*)0x01d70040; /* RTCCON (RTC Control) */<br /> uint32_t volatile* const rtcalm=(uint32_t*)0x01d70050; /* RTCALM (RTC Alarm) */<br /> uint32_t volatile* const almsec=(uint32_t*)0x01d70054; /* ALMSEC (Alarm Second) */<br /> uint32_t volatile* const almmin=(uint32_t*)0x01d70058; /* ALMMIN (Alarm Minute) */<br /> uint32_t volatile* const almhour=(uint32_t*)0x01d7005c; /* ALMHOUR (Alarm Hour) */<br /> uint32_t volatile* const almday=(uint32_t*)0x01d70060; /* ALMDAY (Alarm Day) */<br /> uint32_t volatile* const almmon=(uint32_t*)0x01d70064; /* ALMMON (Alarm Month) */<br /> uint32_t volatile* const almyear=(uint32_t*)0x01d70068; /* ALMYEAR (Alarm Year) */<br /> uint32_t volatile* const rtcrst=(uint32_t*)0x01d7006c; /* RTCRST (RTC Round Reset) */<br /> uint32_t volatile* const bcdsec=(uint32_t*)0x01d70070; /* BCDSEC (BCD Second) */<br /> uint32_t volatile* const bcdmin=(uint32_t*)0x01d70074; /* BCDMIN (BCD Minute) */<br /> uint32_t volatile* const bcdhour=(uint32_t*)0x01d70078; /* BCDHOUR (BCD Hour) */<br /> uint32_t volatile* const bcdday=(uint32_t*)0x01d7007c; /* BCDDAY (BCD Day) */<br /> uint32_t volatile* const bcddate=(uint32_t*)0x01d70080; /* BCDDATE (BCD Date) */<br /> uint32_t volatile* const bcdmon=(uint32_t*)0x01d70084; /* BCDMON (BCD Month) */<br /> uint32_t volatile* const bcdyear=(uint32_t*)0x01d70088; /* BCDYEAR (BCD Year) */<br /> uint32_t volatile* const ticint=(uint32_t*)0x01D7008C; /* TICINT (Tick time count) */<br /> <br /> /****** CLOCK &amp; POWER MANAGEMENT */<br /> uint32_t volatile* const pllcon=(uint32_t*)0x01d80000; /* PLLCON (PLL Control) */<br /> uint32_t volatile* const clkcon=(uint32_t*)0x01d80004; /* CLKCON (Clock Control) */<br /> uint32_t volatile* const clkslow=(uint32_t*)0x01d80008; /* CLKSLOW (Slow clock Control) */<br /> uint32_t volatile* const locktime=(uint32_t*)0x01d8000c; /* LOCKTIME (PLL lock time Counter) */<br /> <br /> /****** INTERRUPT CONTROLLER */<br /> uint32_t volatile* const intcon=(uint32_t*)0x01e00000; /* INTCON (Interrupt Control) */<br /> uint32_t volatile* const intpnd=(uint32_t*)0x01e00004; /* INTPND (Interrupt Request Status) */<br /> uint32_t volatile* const intmod=(uint32_t*)0x01e00008; /* INTMOD (Interrupt Mode Control) */<br /> uint32_t volatile* const intmsk=(uint32_t*)0x01e0000c; /* INTMSK (Interrupt Mask Control) */<br /> uint32_t volatile* const i_pslv=(uint32_t*)0x01e00010; /* I_PSLV (IRQ Interrupt Previous Slave) */<br /> uint32_t volatile* const i_pmst=(uint32_t*)0x01e00014; /* I_PMST (IRQ Interrupt Priority Master) */<br /> uint32_t volatile* const i_cslv=(uint32_t*)0x01e00018; /* I_CSLV (IRQ Interrupt Current Slave) */<br /> uint32_t volatile* const i_cmst=(uint32_t*)0x01e0001c; /* I_CMST (IRQ Interrupt Current Master) */<br /> uint32_t volatile* const i_ispr=(uint32_t*)0x01e00020; /* I_ISPR (IRQ Interrupt Pending Status) */<br /> uint32_t volatile* const i_ispc=(uint32_t*)0x01e00024; /* I_ISPC (IRQ Interrupt Pending Clear) */<br /> uint32_t volatile* const f_ispr=(uint32_t*)0x01e00038; /* F_ISPR (FIQ Interrupt Pending) */<br /> uint32_t volatile* const f_ispc=(uint32_t*)0x01e0003c; /* F_ISPC (FIQ Interrupt Pending Clear) */<br /> <br /> /****** LCD CONTROLLER */<br /> uint32_t volatile* const lcdcon1=(uint32_t*)0x01f00000; /* LCDCON1 (LCD Control 1) */<br /> uint32_t volatile* const lcdcon2=(uint32_t*)0x01f00004; /* LCDCON2 (LCD Control 2) */<br /> uint32_t volatile* const lcdcon3=(uint32_t*)0x01f00040; /* LCDCON3 (LCD Control 3) */<br /> uint32_t volatile* const lcdsaddr1=(uint32_t*)0x01f00008; /* LCDSADDR1 (Frame Upper Buffer Start Address 1) */<br /> uint32_t volatile* const lcdsaddr2=(uint32_t*)0x01f0000c; /* LCDSADDR2 (Frame Lower Buffer Start Address 2) */<br /> uint32_t volatile* const lcdsaddr3=(uint32_t*)0x01f00010; /* LCDSADDR3 (Virtual Screen Address) */<br /> uint32_t volatile* const redlut=(uint32_t*)0x01f00014; /* REDLUT (RED Lookup Table) */<br /> uint32_t volatile* const greenlut=(uint32_t*)0x01f00018; /* GREENLUT (GREEN Lookup Table) */<br /> uint32_t volatile* const bluelut=(uint32_t*)0x01f0001c; /* BLUELUT (BLUE Lookup Table) */<br /> uint32_t volatile* const dp1_2=(uint32_t*)0x01f00020; /* DP1_2 (Dithering Pattern duty 1/2) */<br /> uint32_t volatile* const dp4_7=(uint32_t*)0x01f00024; /* DP4_7 (Dithering Pattern duty 4/7) */<br /> uint32_t volatile* const dp3_5=(uint32_t*)0x01f00028; /* DP3_5 (Dithering Pattern duty 3/5) */<br /> uint32_t volatile* const dp2_3=(uint32_t*)0x01f0002c; /* DP2_3 (Dithering Pattern duty 2/3) */<br /> uint32_t volatile* const dp5_7=(uint32_t*)0x01f00030; /* DP5_7 (Dithering Pattern duty 5/7) */<br /> uint32_t volatile* const dp3_4=(uint32_t*)0x01f00034; /* DP3_4 (Dithering Pattern duty 3/4) */<br /> uint32_t volatile* const dp4_5=(uint32_t*)0x01f00038; /* DP4_5 (Dithering Pattern duty 4/5) */<br /> uint32_t volatile* const dp6_7=(uint32_t*)0x01f0003c; /* DP6_7 (Dithering Pattern duty 6/7) */<br /> uint32_t volatile* const dithmode=(uint32_t*)0x01f00044; /* DITHMODE (Dithering Mode) */<br /> <br /> /****** DMA */<br /> uint32_t volatile* const zdcon0=(uint32_t*)0x01e80000; /* ZDCON0 (ZDMA0 Control) */<br /> uint32_t volatile* const zdisrc0=(uint32_t*)0x01e80004; /* ZDISRC0 (ZDMA 0 Initial Source Address) */<br /> uint32_t volatile* const zdides0=(uint32_t*)0x01e80008; /* ZDIDES0 (ZDMA 0 Initial Destination Address) */<br /> uint32_t volatile* const zdicnt0=(uint32_t*)0x01e8000c; /* ZDICNT0 (ZDMA 0 Initial Transfer Count) */<br /> uint32_t volatile* const zdcsrc0=(uint32_t*)0x01e80010; /* ZDCSRC0 (ZDMA 0 Current Source Address) */<br /> uint32_t volatile* const zdcdes0=(uint32_t*)0x01e80014; /* ZDCDES0 (ZDMA 0 Current Destination Address) */<br /> uint32_t volatile* const zdccnt0=(uint32_t*)0x01e80018; /* ZDCCNT0 (ZDMA 0 Current Transfer Count) */<br /> uint32_t volatile* const zdcon1=(uint32_t*)0x01e80020; /* ZDCON1 (ZDMA 1 Control) */<br /> uint32_t volatile* const zdisrc1=(uint32_t*)0x01e80024; /* ZDISRC1 (ZDMA 1 Initial Source Address) */<br /> uint32_t volatile* const zdides1=(uint32_t*)0x01e80028; /* ZDIDES1 (ZDMA 1 Initial Destination Address) */<br /> uint32_t volatile* const zdicnt1=(uint32_t*)0x01e8002c; /* ZDICNT1 (ZDMA 1 Initial Transfer Count) */<br /> uint32_t volatile* const zdcsrc1=(uint32_t*)0x01e80030; /* ZDCSRC1 (ZDMA 1 Current Source Address) */<br /> uint32_t volatile* const zdcdes1=(uint32_t*)0x01e80034; /* ZDCDES1 (ZDMA 1 Current Destination Address) */<br /> uint32_t volatile* const zdccnt1=(uint32_t*)0x01e80038; /* ZDCCNT1 (ZDMA 1 Current Transfer Count) */<br /> uint32_t volatile* const bdcon0=(uint32_t*)0x01f80000; /* BDCON0 (BDMA 0 Control) */<br /> uint32_t volatile* const bdisrc0=(uint32_t*)0x01f80004; /* BDISRC0 (BDMA 0 Initial Source Address) */<br /> uint32_t volatile* const bdides0=(uint32_t*)0x01f80008; /* BDIDES0 (BDMA 0 Initial Destination Address) */<br /> uint32_t volatile* const bdicnt0=(uint32_t*)0x01f8000c; /* BDICNT0 (BDMA 0 Initial Transfer Count) */<br /> uint32_t volatile* const bdcsrc0=(uint32_t*)0x01f80010; /* BDCSRC0 (BDMA 0 Current Source Address) */<br /> uint32_t volatile* const bdcdes0=(uint32_t*)0x01f80014; /* BDCDES0 (BDMA 0 Current Destination Address) */<br /> uint32_t volatile* const bdccnt0=(uint32_t*)0x01f80018; /* BDCCNT0 (BDMA 0 Current Transfer Count) */<br /> uint32_t volatile* const bdcon1=(uint32_t*)0x01f80020; /* BDCON1 (BDMA 1 Control) */<br /> uint32_t volatile* const bdisrc1=(uint32_t*)0x01f80024; /* BDISRC1 (BDMA 1 Initial Source Address) */<br /> uint32_t volatile* const bdides1=(uint32_t*)0x01f80028; /* BDIDES1 (BDMA 1 Initial Destination Address) */<br /> uint32_t volatile* const bdicnt1=(uint32_t*)0x01f8002c; /* BDICNT1 (BDMA 1 Initial Transfer Count) */<br /> uint32_t volatile* const bdcsrc1=(uint32_t*)0x01f80030; /* BDCSRC1 (BDMA 1 Current Source Address) */<br /> uint32_t volatile* const bdcdes1=(uint32_t*)0x01f80034; /* BDCDES1 (BDMA 1 Current Destination Address) */<br /> uint32_t volatile* const bdccnt1=(uint32_t*)0x01f80038; /* BDCCNT1 (BDMA 1 Current Transfer Count) */<br /> <br /> &lt;/pre&gt;</div>

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