Difference between revisions of "LF-1000"
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| − | + | = Summary = | |
OEM branded version of the MagicEyes [[Pollux]] VF3520F [[media:pollux-datasheet.pdf|Datasheet]] | OEM branded version of the MagicEyes [[Pollux]] VF3520F [[media:pollux-datasheet.pdf|Datasheet]] | ||
<br> | <br> | ||
| − | == | + | == Core == |
| − | + | *ARM926EJ-S- 393MHz | |
| + | **16KByte I-Cache | ||
| + | **16KByte D-Cache | ||
| + | **High performance 32bit CPU Core | ||
| + | **Jazelle Java Hardware Accelerator | ||
| + | *90 nm Process | ||
| + | *288pin FBGA | ||
| + | *15mm x 15mm | ||
| + | *0.65mm pitch | ||
| − | + | == Memory == | |
| − | + | *DDR SDRAM Controller | |
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| − | DDR SDRAM Controller | + | |
*133MHz DDR SDRAM memory x 16bit | *133MHz DDR SDRAM memory x 16bit | ||
*Single DDR memory bank | *Single DDR memory bank | ||
*Up to 128MB | *Up to 128MB | ||
*Peak Memory Bandwidth : 533MByte/sec | *Peak Memory Bandwidth : 533MByte/sec | ||
| + | *8 Channel DMA | ||
| − | + | == Storage == | |
| − | + | *Static Bus controller | |
| − | + | *16 bit data bus | |
| − | + | *SLC/ MLC NAND Support | |
| − | Static Bus controller | + | *8 bit NAND flash |
| − | 16 bit data bus | + | *8/16 bit SRAM Support |
| − | 8 bit NAND flash | + | *Boot form NAND flash NOR flash |
| − | + | *IDE interface with PIO mode | |
| − | Boot form NAND flash NOR flash | + | *SD/ MMC interface |
| − | IDE interface with PIO mode | + | **Two Channels of SD/MMC |
| − | + | **SD mem Version 2.00 | |
| − | + | **SDIO version 1.10 | |
| − | Two Channels of SD/MMC | + | **MMC version 4.2 |
| − | SD mem Version 2.00 | + | **clock speed up to 52MHz |
| − | SDIO version 1.10 | + | **PIO and DMA mode data transfer |
| − | MMC version 4.2 | + | |
| − | clock speed up to 52MHz | + | |
| − | PIO and DMA mode data transfer | + | |
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| + | ==3D Graphic Accelerator == | ||
| + | 3D Performance : 133M Texel/sec, 1.33M Polygon/sec<br> | ||
| + | OpenGL ES 1.1 Compatible<br> | ||
| + | 512-depth instruction memory<br> | ||
| + | 256 Vector Input/Constant Registers<br> | ||
| + | 16 Vector General Purpose Registers<br> | ||
| + | 2x2 Sub-Pixel Accuracy<br> | ||
| + | Per-Pixel Fogging<br> | ||
| + | Hardware Dithering<br> | ||
Texture Features | Texture Features | ||
*Perspective Correction | *Perspective Correction | ||
| Line 66: | Line 54: | ||
*MIPMAP | *MIPMAP | ||
| − | + | == Display Subsystem == | |
| − | + | Onboard TFT controller<br> | |
| − | + | ||
| − | + | ||
* Support for screens with a size up to 1280 * 1024@60Hz | * Support for screens with a size up to 1280 * 1024@60Hz | ||
* Supports Flat Panel I/F: Color TFT at 16, 18, 24 bit//Pixel, STN-LCD | * Supports Flat Panel I/F: Color TFT at 16, 18, 24 bit//Pixel, STN-LCD | ||
| Line 83: | Line 69: | ||
*** Independent Dual Display Output | *** Independent Dual Display Output | ||
| − | + | == Integrated peripherals == | |
| − | + | === USB === | |
| − | + | ||
| − | + | ||
USB Host 1.1 | USB Host 1.1 | ||
*3 downstream ports | *3 downstream ports | ||
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*Support FS/HS dual mode operation | *Support FS/HS dual mode operation | ||
| − | + | === I2C interface === | |
2 channel I2C-bus | 2 channel I2C-bus | ||
100Kbps ~ 1Mbps Speed | 100Kbps ~ 1Mbps Speed | ||
| − | + | === Other === | |
4Ch UART, | 4Ch UART, | ||
SSP/ SPI interface | SSP/ SPI interface | ||
| Line 104: | Line 88: | ||
JTAG | JTAG | ||
| − | + | == Power Management == | |
| − | + | ||
*Individual block dynamic power controlller | *Individual block dynamic power controlller | ||
* Supports various power down mode | * Supports various power down mode | ||
** Idle | ** Idle | ||
** Stop | ** Stop | ||
| − | + | == Operating Temperature == | |
| − | + | ||
* 0℃ ~ 70℃ | * 0℃ ~ 70℃ | ||
| − | + | == Operating Systems == | |
* Microsoft Windows CE 5.0/6.0 | * Microsoft Windows CE 5.0/6.0 | ||
* Linux | * Linux | ||
| + | |||
| + | [[Category:Hardware]] | ||
Latest revision as of 08:36, 28 October 2011
Contents |
Summary
OEM branded version of the MagicEyes Pollux VF3520F Datasheet
Core
- ARM926EJ-S- 393MHz
- 16KByte I-Cache
- 16KByte D-Cache
- High performance 32bit CPU Core
- Jazelle Java Hardware Accelerator
- 90 nm Process
- 288pin FBGA
- 15mm x 15mm
- 0.65mm pitch
Memory
- DDR SDRAM Controller
- 133MHz DDR SDRAM memory x 16bit
- Single DDR memory bank
- Up to 128MB
- Peak Memory Bandwidth : 533MByte/sec
- 8 Channel DMA
Storage
- Static Bus controller
- 16 bit data bus
- SLC/ MLC NAND Support
- 8 bit NAND flash
- 8/16 bit SRAM Support
- Boot form NAND flash NOR flash
- IDE interface with PIO mode
- SD/ MMC interface
- Two Channels of SD/MMC
- SD mem Version 2.00
- SDIO version 1.10
- MMC version 4.2
- clock speed up to 52MHz
- PIO and DMA mode data transfer
3D Graphic Accelerator
3D Performance : 133M Texel/sec, 1.33M Polygon/sec
OpenGL ES 1.1 Compatible
512-depth instruction memory
256 Vector Input/Constant Registers
16 Vector General Purpose Registers
2x2 Sub-Pixel Accuracy
Per-Pixel Fogging
Hardware Dithering
Texture Features
- Perspective Correction
- Multi-Texturing
- Bi-Linear Filtering
- MIPMAP
Display Subsystem
Onboard TFT controller
- Support for screens with a size up to 1280 * 1024@60Hz
- Supports Flat Panel I/F: Color TFT at 16, 18, 24 bit//Pixel, STN-LCD
- Display Layers
- RGB Layer : 2 Layer, 8/16/24bpp Format
- YUV Layer : YUV4:2:0, 2D/Linear Format, Scale Up/Down
- Effects : Color Key, Priority, Alpha Blending(16 Levels)
- Color Control : Brightness, Contrast, Hue, Saturation
- Output Format
- CCIR 601/656, RGB, M-RGB(Multiplexed RGB)
- Supports NTSC/PAL Encoder with Analog DAC
- CVBS Output
- Independent Dual Display Output
- Display Layers
Integrated peripherals
USB
USB Host 1.1
- 3 downstream ports
USB 2.0 Device
- Support FS/HS dual mode operation
I2C interface
2 channel I2C-bus 100Kbps ~ 1Mbps Speed
Other
4Ch UART, SSP/ SPI interface ADC PWM JTAG
Power Management
- Individual block dynamic power controlller
- Supports various power down mode
- Idle
- Stop
Operating Temperature
- 0℃ ~ 70℃
Operating Systems
- Microsoft Windows CE 5.0/6.0
- Linux
