Difference between revisions of "Minnowboard:Expansion Interfaces"

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Line 15: Line 15:
 
| 3 || style="background:#8f99b1" | 4 || style="background:#8f99b1" | HDA_CLK
 
| 3 || style="background:#8f99b1" | 4 || style="background:#8f99b1" | HDA_CLK
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 5 || style="background:#8f99b1" | 6 || style="background:#8f99b1" | HDA_RST_N
 
| 5 || style="background:#8f99b1" | 6 || style="background:#8f99b1" | HDA_RST_N
 
|- style="background:#b783a7"
 
|- style="background:#b783a7"
Line 24: Line 24:
 
| 9 || style="background:#8f99b1" | 10 || style="background:#8f99b1" | HDA_SDO
 
| 9 || style="background:#8f99b1" | 10 || style="background:#8f99b1" | HDA_SDO
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 11 || style="background:#8f99b1" | 12 || style="background:#8f99b1" | HDA_SDI1
 
| 11 || style="background:#8f99b1" | 12 || style="background:#8f99b1" | HDA_SDI1
 
|- style="background:#b783a7"
 
|- style="background:#b783a7"
 
| [[#pcie | PCIe1_RX_N]]
 
| [[#pcie | PCIe1_RX_N]]
| 13 || style="background:green" | 14 || style="background:green" | GND
+
| 13 || style="background:green" | 14 || style="background:green" | [[#gnd | GND]]
 
|- style="background:#b783a7"
 
|- style="background:#b783a7"
 
| [[#pcie | PCIe1_RX_P]]
 
| [[#pcie | PCIe1_RX_P]]
 
| 15 || style="background:#b783a7" | 16 || style="background:#b783a7" | [[#pcie | PCIe2_RX_N]]
 
| 15 || style="background:#b783a7" | 16 || style="background:#b783a7" | [[#pcie | PCIe2_RX_N]]
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 17 || style="background:#b783a7" | 18 || style="background:#b783a7" | [[#pcie | PCIe2_RX_P]]
 
| 17 || style="background:#b783a7" | 18 || style="background:#b783a7" | [[#pcie | PCIe2_RX_P]]
 
|- style="background:#b783a7"
 
|- style="background:#b783a7"
Line 39: Line 39:
 
| 19
 
| 19
 
| 20
 
| 20
| GND
+
| [[#gnd | GND]]
 
|- style="background:#b783a7"
 
|- style="background:#b783a7"
 
| [[#pcie | PCIe1_TX_P]]
 
| [[#pcie | PCIe1_TX_P]]
 
| 21 || style="background:#b783a7" | 22 || style="background:#b783a7" | [[#pcie | PCIe2_TX_N]]
 
| 21 || style="background:#b783a7" | 22 || style="background:#b783a7" | [[#pcie | PCIe2_TX_N]]
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 23 || style="background:#b783a7" | 24 || style="background:#b783a7" | [[#pcie | PCIe2_TX_P]]
 
| 23 || style="background:#b783a7" | 24 || style="background:#b783a7" | [[#pcie | PCIe2_TX_P]]
 
|- style="background:#00ff3c"
 
|- style="background:#00ff3c"
 
| SMB_CLK
 
| SMB_CLK
| 25 || style="background:green" | 26 || style="background:green" | GND
+
| 25 || style="background:green" | 26 || style="background:green" | [[#gnd | GND]]
 
|- style="background:#00ff3c"
 
|- style="background:#00ff3c"
 
| SMB_DAT
 
| SMB_DAT
Line 54: Line 54:
 
| style="background:#7816E7" | [[#canbus | '''CAN_TX''']]
 
| style="background:#7816E7" | [[#canbus | '''CAN_TX''']]
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 29 || style="background:#7816E7" | 30  
 
| 29 || style="background:#7816E7" | 30  
 
| style="background:#7816E7" | [[#canbus | '''CAN_RX''']]
 
| style="background:#7816E7" | [[#canbus | '''CAN_RX''']]
 
|- style="background:#2099FF"
 
|- style="background:#2099FF"
 
| SATA1_RX_N
 
| SATA1_RX_N
| 31 || style="background:green" | 32 || style="background:green" | GND
+
| 31 || style="background:green" | 32 || style="background:green" | [[#gnd | GND]]
 
|- style="background:#2099FF"
 
|- style="background:#2099FF"
 
| SATA1_RX_P
 
| SATA1_RX_P
 
| 33 || style="background:#DCC842" | 34 || style="background:#DCC842" | LVDS_DATA_N_0
 
| 33 || style="background:#DCC842" | 34 || style="background:#DCC842" | LVDS_DATA_N_0
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 35 || style="background:#DCC842" | 36 || style="background:#DCC842" | LVDS_DATA_P_0
 
| 35 || style="background:#DCC842" | 36 || style="background:#DCC842" | LVDS_DATA_P_0
 
|- style="background:#2099FF"
 
|- style="background:#2099FF"
 
| SATA1_TX_N
 
| SATA1_TX_N
| 37 || style="background:green" | 38 || style="background:green" | GND
+
| 37 || style="background:green" | 38 || style="background:green" | [[#gnd | GND]]
 
|- style="background:#2099FF"
 
|- style="background:#2099FF"
 
| SATA1_TX_P
 
| SATA1_TX_P
 
| 39 || style="background:#DCC842" | 40 || style="background:#DCC842" | LVDS_DATA_N_1
 
| 39 || style="background:#DCC842" | 40 || style="background:#DCC842" | LVDS_DATA_N_1
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 41 || style="background:#DCC842" | 42 || style="background:#DCC842" | LVDS_DATA_P_1
 
| 41 || style="background:#DCC842" | 42 || style="background:#DCC842" | LVDS_DATA_P_1
 
|- style="background:#70b1a1"
 
|- style="background:#70b1a1"
Line 85: Line 85:
 
| 47 || style="background:#DCC842" | 48 || style="background:#DCC842" | LVDS_DATA_P_2
 
| 47 || style="background:#DCC842" | 48 || style="background:#DCC842" | LVDS_DATA_P_2
 
|- style="background:green"
 
|- style="background:green"
| GND
+
| [[#gnd | GND]]
 
| 49
 
| 49
 
| 50
 
| 50
| GND
+
| [[#gnd | GND]]
 
|- style="background:#f1e914"
 
|- style="background:#f1e914"
 
| WAKE_EXP_N
 
| WAKE_EXP_N
Line 186: Line 186:
 
http://www.partssource.com/site/ControllerAreaNetwork
 
http://www.partssource.com/site/ControllerAreaNetwork
  
== <span id="pcie" style="color:#b783a7;">PCIe</span> ==
+
== <span id="pcie" style="color:#b783a7">PCIe</span> ==
 
PCI Express (PCIe or PCI-E) is a high-speed, serial computer expansion bus standard that connects a computer with its attached peripherals. PCI Express was developed by Intel Corp. in 2004 to replace the peripheral component interconnect (PCI) and PCI-X expansion buses, along with the accelerated graphics port (AGP) graphics card interface. Today, PCI Express is the primary connection method for most video cards to modern computers. For more information refer the link below:
 
PCI Express (PCIe or PCI-E) is a high-speed, serial computer expansion bus standard that connects a computer with its attached peripherals. PCI Express was developed by Intel Corp. in 2004 to replace the peripheral component interconnect (PCI) and PCI-X expansion buses, along with the accelerated graphics port (AGP) graphics card interface. Today, PCI Express is the primary connection method for most video cards to modern computers. For more information refer the link below:
  
 
http://www.hardwaresecrets.com/article/190
 
http://www.hardwaresecrets.com/article/190
  
== <span id="gnd" style="color:#b783a7;">GND</span> ==
+
== <span id="gnd" style="color:green">GND</span> ==
 
GND or Ground is simply a reference voltage level(called zero potential or ground potential) against which all other voltages in a system are established and measured.
 
GND or Ground is simply a reference voltage level(called zero potential or ground potential) against which all other voltages in a system are established and measured.
 +
 +
  
  

Revision as of 14:19, 15 May 2013

The table below describes the various different expansion interfaces on the Minnowboard:

Expansion Interfaces on the Minnowboard
Function Pin Number Pin Number Function
PCIe1_CLK_REQ 1 2 PCIe2_CLK_REQ
PWROK 3 4 HDA_CLK
GND 5 6 HDA_RST_N
PCIe_REFCLK_N 7 8 HDA_SYNC
PCIe_REFCLK_P 9 10 HDA_SDO
GND 11 12 HDA_SDI1
PCIe1_RX_N 13 14 GND
PCIe1_RX_P 15 16 PCIe2_RX_N
GND 17 18 PCIe2_RX_P
PCIe1_TX_N 19 20 GND
PCIe1_TX_P 21 22 PCIe2_TX_N
GND 23 24 PCIe2_TX_P
SMB_CLK 25 26 GND
SMB_DAT 27 28 CAN_TX
GND 29 30 CAN_RX
SATA1_RX_N 31 32 GND
SATA1_RX_P 33 34 LVDS_DATA_N_0
GND 35 36 LVDS_DATA_P_0
SATA1_TX_N 37 38 GND
SATA1_TX_P 39 40 LVDS_DATA_N_1
GND 41 42 LVDS_DATA_P_1
USB_HOST_DM4 43 44 GND
USB_HOST_DP4 45 46 LVDS_DATA_N_2
VBUS4 47 48 LVDS_DATA_P_2
GND 49 50 GND
WAKE_EXP_N 51 52 LVDS_CLK_N
UART1_TX 53 54 LVDS_CLK_P
UART1_RX 55 56 GND
UART2_TX 57 58 LVDS_DATA_N_3
UART2_RX 59 60 LVDS_DATA_P_3
I2C0_SCL 61 62 GND
I2C0_SDA 63 64 E6XX_GPIO_SUS0
GND 65 66 E6XX_GPIO_SUS1
EG20T_SPI_CLK 67 68 E6XX_GPIO_SUS3
EG20T_SPI_nCS 69 70 E6XX_GPIO_SUS4
EG20T_SPI_MOSI 71 72 E6XX_GPIO_SUS2
EG20T_SPI_MISO 73 74 LVDS_DETECT
GPIO0 75 76 SDIO1_CD_N
GPIO1 77 78 SDIO1_WP
GPIO2 79 80 SDIO1_CLK_R
GPIO3 81 82 SDIO1_CMD_R
GPIO4 83 84 SDIO1_DATA0_R
GPIO5 85 86 SDIO1_DATA1_R
GPIO6 87 88 SDIO1_DATA2_R
GPIO7 89 90 SDIO1_DATA3_R
GPIO_PROG_VOLTAGE 91 92 DC_IN_5V
DC_IN_5V 93 94 DC_IN_5V
DC_IN_5V 95 96 DC_IN_5V
DC_IN_5V 97 98 DC_IN_5V
DC_IN_5V 99 100 DC_IN_5V

+5V Power

This is the primary input from the external power jack!

General Purpose Input/Output

These are GPIOs that can be used for basic input and output.

CAN

Controller Area Network(CAN), or as it is commonly known, CAN-bus, is a communication protocol originally designed for automotive applications. It is an asynchronous serial bus network that connects devices, sensors and actuators for control applications. CAN is now standardized in ISO 11898, ISO 16845 and SAE J1939 for automotive, industrial and general embedded communications. CAN-bus is now commonly employed not only in automotive and aerospace applications but also in medical equipment. For more information, please refer the link below:

http://www.partssource.com/site/ControllerAreaNetwork

PCIe

PCI Express (PCIe or PCI-E) is a high-speed, serial computer expansion bus standard that connects a computer with its attached peripherals. PCI Express was developed by Intel Corp. in 2004 to replace the peripheral component interconnect (PCI) and PCI-X expansion buses, along with the accelerated graphics port (AGP) graphics card interface. Today, PCI Express is the primary connection method for most video cards to modern computers. For more information refer the link below:

http://www.hardwaresecrets.com/article/190

GND

GND or Ground is simply a reference voltage level(called zero potential or ground potential) against which all other voltages in a system are established and measured.