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Omap3530.cfg - Revision history
2013-06-19T09:52:10Z
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Wmat: omap3530.cfg
2012-05-08T15:50:27Z
<p>omap3530.cfg</p>
<p><b>New page</b></p><div><syntaxhighlight code="tcl"><br />
# TI OMAP3530<br />
# http://focus.ti.com/docs/prod/folders/print/omap3530.html<br />
# Other OMAP3 chips remove DSP and/or the OpenGL support<br />
<br />
if { [info exists CHIPNAME] } {<br />
set _CHIPNAME $CHIPNAME<br />
} else {<br />
set _CHIPNAME omap3530<br />
}<br />
<br />
# ICEpick-C ... used to route Cortex, DSP, and more not shown here<br />
source [find target/icepick.cfg]<br />
<br />
# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick<br />
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable<br />
<br />
# Subsidiary TAP: CoreSight Debug Access Port (DAP)<br />
if { [info exists DAP_TAPID] } {<br />
set _DAP_TAPID $DAP_TAPID<br />
} else {<br />
set _DAP_TAPID 0x0b6d602f<br />
}<br />
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \<br />
-expected-id $_DAP_TAPID -disable<br />
jtag configure $_CHIPNAME.dap -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 3"<br />
<br />
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan<br />
if { [info exists JRC_TAPID] } {<br />
set _JRC_TAPID $JRC_TAPID<br />
} else {<br />
set _JRC_TAPID 0x0b7ae02f<br />
}<br />
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \<br />
-expected-id $_JRC_TAPID<br />
<br />
# GDB target: Cortex-A8, using DAP<br />
set _TARGETNAME $_CHIPNAME.cpu<br />
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap<br />
<br />
# SRAM: 64K at 0x4020.0000; use the first 16K<br />
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000<br />
<br />
###################<br />
<br />
# the reset sequence is event-driven<br />
# and kind of finicky...<br />
<br />
# some TCK tycles are required to activate the DEBUG power domain<br />
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"<br />
<br />
# have the DAP "always" be active<br />
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"<br />
<br />
proc omap3_dbginit {target} {<br />
# General Cortex A8 debug initialisation<br />
cortex_a8 dbginit<br />
# Enable DBGU signal for OMAP353x<br />
$target mww phys 0x5401d030 0x00002000<br />
}<br />
<br />
# be absolutely certain the JTAG clock will work with the worst-case<br />
# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.<br />
# OK to speed up *after* PLL and clock tree setup.<br />
jtag_rclk 1000<br />
$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }<br />
<br />
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset<br />
# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick<br />
# would issue. RST_DPLL3 (4) is a cold reset.<br />
set PRM_RSTCTRL 0x48307250<br />
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww $PRM_RSTCTRL 2"<br />
<br />
$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"<br />
</syntaxhighlight><br />
<br />
[[Category:OpenOCD]]<br />
[[Category:Debugging]]<br />
[[Category:TinCanTools]]</div>
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