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Omap4430.cfg - Revision history
2013-05-20T05:40:16Z
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Wmat: omap4430.cfg
2012-05-08T15:52:01Z
<p>omap4430.cfg</p>
<p><b>New page</b></p><div><syntaxhighlight code="tcl"><br />
# OMAP4430<br />
<br />
if { [info exists CHIPNAME] } {<br />
set _CHIPNAME $CHIPNAME<br />
} else {<br />
set _CHIPNAME omap4430<br />
}<br />
<br />
<br />
# Although the OMAP4430 supposedly has an ICEpick-D, only the<br />
# ICEpick-C router commands seem to work.<br />
# See http://processors.wiki.ti.com/index.php/ICEPICK<br />
source [find target/icepick.cfg]<br />
<br />
<br />
#<br />
# A9 DAP<br />
#<br />
if { [info exists DAP_TAPID] } {<br />
set _DAP_TAPID $DAP_TAPID<br />
} else {<br />
set _DAP_TAPID 0x3BA00477<br />
}<br />
<br />
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \<br />
-expected-id $_DAP_TAPID -disable<br />
jtag configure $_CHIPNAME.dap -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 9"<br />
<br />
<br />
#<br />
# M3 DAPs, one per core<br />
#<br />
if { [info exists M3_DAP_TAPID] } {<br />
set _M3_DAP_TAPID $M3_DAP_TAPID<br />
} else {<br />
set _M3_DAP_TAPID 0x4BA00477<br />
}<br />
<br />
jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \<br />
-expected-id $_M3_DAP_TAPID -disable<br />
jtag configure $_CHIPNAME.m31_dap -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 5"<br />
<br />
jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \<br />
-expected-id $_M3_DAP_TAPID -disable<br />
jtag configure $_CHIPNAME.m30_dap -event tap-enable \<br />
"icepick_c_tapenable $_CHIPNAME.jrc 4"<br />
<br />
<br />
#<br />
# ICEpick-D JRC (JTAG route controller)<br />
#<br />
if { [info exists JRC_TAPID] } {<br />
set _JRC_TAPID $JRC_TAPID<br />
} else {<br />
set _JRC_TAPID 0x3b95c02f<br />
set _JRC_TAPID2 0x1b85202f<br />
}<br />
<br />
# PandaBoard REV EA1 (PEAP platforms)<br />
if { [info exists JRC_TAPID2] } {<br />
set _JRC_TAPID2 $JRC_TAPID2<br />
} else {<br />
set _JRC_TAPID2 0x1b85202f<br />
}<br />
<br />
<br />
<br />
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \<br />
-expected-id $_JRC_TAPID -expected-id $_JRC_TAPID2<br />
<br />
# Required by ICEpick to power-up the debug domain<br />
jtag configure $_CHIPNAME.jrc -event post-reset "runtest 200"<br />
<br />
<br />
#<br />
# GDB target: Cortex-A9, using DAP<br />
#<br />
# The debugger can connect to either core of the A9, but currently<br />
# not both simultaneously. Change -coreid to 1 to connect to the<br />
# second core.<br />
#<br />
set _TARGETNAME $_CHIPNAME.cpu<br />
<br />
# APB DBGBASE reads 0x80040000, but this points to an empty ROM table.<br />
# 0x80000000 is cpu0 coresight region<br />
#<br />
#<br />
# CORTEX_A8_PADDRDBG_CPU_SHIFT 13<br />
# 0x80000000 | (coreid << CORTEX_A8_PADDRDBG_CPU_SHIFT)<br />
<br />
set _coreid 0<br />
set _dbgbase [expr 0x80000000 | ($_coreid << 13)]<br />
echo "Using dbgbase = [format 0x%x $_dbgbase]"<br />
<br />
target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap \<br />
-coreid 0 -dbgbase $_dbgbase<br />
<br />
# SRAM: 56KiB at 0x4030.0000<br />
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000<br />
<br />
<br />
#<br />
# M3 targets, separate TAP/DAP for each core<br />
#<br />
target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap<br />
target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap<br />
<br />
<br />
# Once the JRC is up, enable our TAPs<br />
jtag configure $_CHIPNAME.jrc -event setup "<br />
jtag tapenable $_CHIPNAME.dap<br />
jtag tapenable $_CHIPNAME.m30_dap<br />
jtag tapenable $_CHIPNAME.m31_dap<br />
"<br />
<br />
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset<br />
# ourselves using PRM_RSTCTRL. 1 is a warm reset, 2 a cold reset.<br />
set PRM_RSTCTRL 0x4A307B00<br />
$_TARGETNAME configure -event reset-assert "$_TARGETNAME mww phys $PRM_RSTCTRL 0x1"<br />
$_CHIPNAME.m30 configure -event reset-assert { }<br />
$_CHIPNAME.m31 configure -event reset-assert { }<br />
<br />
# Soft breakpoints don't currently work due to broken cache handling<br />
gdb_breakpoint_override hard<br />
<br />
</syntaxhighlight><br />
<br />
[[Category:OpenOCD]]<br />
[[Category:Debugging]]<br />
[[Category:TinCanTools]]</div>
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