- halt, single-step, resume
- breakpoints and watchpoints
- reading/writing memory
- inspecting core/register state
All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed. This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs).
- debugging A9 cores simultaneously
- accessing L2 memory resources
- unify a8/a9 code
The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking. If your debugger can identify JTAG devices, e.g.:
Info : 375 316 core.c:948 jtag_examine_chain_display(): JTAG tap: omap4430.jrc tap/device found: 0x3b95c02f (mfg: 0x017, part: 0xb95c, ver: 0x3)
but no Cortex-A9 target appears, you are probably running into this issue. Verify by connecting the debugger with no SD card inserted: if it now works, you're hitting this issue.
The current x-loader mainline includes a workaround.