Scribe: Initial draft

2011-11-30T21:47:12Z

Initial draft

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== Local Data Memory Map ==
The following memory mappings may only be used from within the PRUSS.

{|style="border-collapse: separate; border-spacing: 0; border-width: 1px; border-style: solid; border-color: #000; padding: 0;"
|-
!style="width: 200px; border-style: solid; border-width: 0 1px 1px 0"| Start Address
!style="width: 200px; border-style: solid; border-width: 0 1px 1px 0"| PRU0
!style="width: 200px; border-style: solid; border-width: 0 1px 1px 0"| PRU1
!style="width: 600px; text-align: center; border-style: solid; border-width: 0 0 1px 0"| Description
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0000_0000
|style="border-style: solid; border-width: 0 1px 1px 0"| Data 8KB RAM 0
|style="border-style: solid; border-width: 0 1px 1px 0"| Data 8KB RAM 1
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| 8KB data RAM belonging to PRU0
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0000_2000
|style="border-style: solid; border-width: 0 1px 1px 0"| Data 8KB RAM 1
|style="border-style: solid; border-width: 0 1px 1px 0"| Data 8KB RAM 0
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| 8KB data RAM belonging to PRU1
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0001_0000
|style="border-style: solid; border-width: 0 1px 1px 0"| Data 12KB RAM 2 (Shared)
|style="border-style: solid; border-width: 0 1px 1px 0"| Data 12KB RAM 2 (Shared)
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| 12KB data RAM shared between both PRUs
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_0000
|style="border-style: solid; border-width: 0 1px 1px 0"| INTC
|style="border-style: solid; border-width: 0 1px 1px 0"| INTC
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0002_2000
|style="border-style: solid; border-width: 0 1px 0 0"| PRU0 Control Registers
|style="border-style: solid; border-width: 0 1px 0 0"| PRU0 Control Registers
|style="border-style: solid; text-align: center; border-width: 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_2400
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| -
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0002_4000
|style="border-style: solid; border-width: 0 1px 0 0"| PRU1 Control Registers
|style="border-style: solid; border-width: 0 1px 0 0"| PRU1 Control Registers
|style="border-style: solid; text-align: center; border-width: 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_4400
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| -
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_6000
|style="border-style: solid; border-width: 0 1px 1px 0"| CFG
|style="border-style: solid; border-width: 0 1px 1px 0"| CFG
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0002_8000
|style="border-style: solid; border-width: 0 1px 0 0"| UART 0
|style="border-style: solid; border-width: 0 1px 0 0"| UART 0
|style="border-style: solid; text-align: center; border-width: 0"| PRUSS dedicated UART Controller (Universal Asynchronous Receive/Transmit Controller)
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0002_A000
|style="border-style: solid; border-width: 0 1px 0 0"| Reserved
|style="border-style: solid; border-width: 0 1px 0 0"| Reserved
|style="border-style: solid; text-align: center; border-width: 0"| -
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_C000
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| -
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_E000
|style="border-style: solid; border-width: 0 1px 1px 0"| IEP
|style="border-style: solid; border-width: 0 1px 1px 0"| IEP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0003_0000
|style="border-style: solid; border-width: 0 1px 1px 0"| eCAP 0
|style="border-style: solid; border-width: 0 1px 1px 0"| eCAP 0
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0003_2000
|style="border-style: solid; border-width: 0 1px 0 0"| MII_RT_CFG
|style="border-style: solid; border-width: 0 1px 0 0"| MII_RT_CFG
|style="border-style: solid; text-align: center; border-width: 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0003_2400
|style="border-style: solid; border-width: 0 1px 0 0"| MII_MDIO
|style="border-style: solid; border-width: 0 1px 0 0"| MII_MDIO
|style="border-style: solid; text-align: center; border-width: 0"| ?
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0003_4000
|style="border-style: solid; border-width: 0 1px 0 0"| Reserved
|style="border-style: solid; border-width: 0 1px 0 0"| Reserved
|style="border-style: solid; text-align: center; border-width: 0"| -
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0003_8000
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; border-width: 0 1px 1px 0"| Reserved
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| -
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0004_0000
|style="border-style: solid; border-width: 0 1px 0 0"| Reserved
|style="border-style: solid; border-width: 0 1px 0 0"| Reserved
|style="border-style: solid; text-align: center; border-width: 0"| -
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0008_0000
|style="border-style: solid; border-width: 0 1px 0 0"| System OCP_HP0
|style="border-style: solid; border-width: 0 1px 0 0"| System OCP_HP1
|style="border-style: solid; text-align: center; border-width: 0"| Address Offset of the Interface/OCP Master Port used to access the host memory map
|}

== Global Memory Map ==
The following memory mappings may be used either from the host ARM Cortex-A8 CPU or from within the PRUSS.

''It is recommended to use local mappings from within the PRUSS however, as access times will be faster.''

{|style="border-collapse: separate; border-spacing: 0; border-width: 1px; border-style: solid; border-color: #000; padding: 0;"
|-
!style="width: 300px; border-style: solid; border-width: 0 1px 1px 0"| Offset Address
!style="width: 300px; border-style: solid; border-width: 0 0 1px 0"| PRUSS
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0000_0000
|style="border-style: solid; border-width: 0 0 1px 0"| Data 8KB RAM 0
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0000_2000
|style="border-style: solid; border-width: 0 0 1px 0"| Data 8KB RAM 1
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0001_0000
|style="border-style: solid; border-width: 0 0 1px 0"| Data 12KB RAM 2 (Shared)
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_0000
|style="border-style: solid; border-width: 0 0 1px 0"| INTC
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_2000
|style="border-style: solid; border-width: 0 0 1px 0"| PRU0 Control
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_2400
|style="border-style: solid; border-width: 0 0 1px 0"| PRU0 Debug
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_4000
|style="border-style: solid; border-width: 0 0 1px 0"| PRU1 Control
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_4400
|style="border-style: solid; border-width: 0 0 1px 0"| PRU1 Debug
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_6000
|style="border-style: solid; border-width: 0 0 1px 0"| CFG
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_8000
|style="border-style: solid; border-width: 0 0 1px 0"| UART 0
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_A000
|style="border-style: solid; border-width: 0 0 1px 0"| Reserved
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_C000
|style="border-style: solid; border-width: 0 0 1px 0"| Reserved
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0002_E000
|style="border-style: solid; border-width: 0 0 1px 0"| IEP
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0003_0000
|style="border-style: solid; border-width: 0 0 1px 0"| eCAP 0
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0003_2000
|style="border-style: solid; border-width: 0 0 1px 0"| MII_RT_CFG
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0003_2400
|style="border-style: solid; border-width: 0 0 1px 0"| MII_MDIO
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0003_4000
|style="border-style: solid; border-width: 0 0 1px 0"| PRU0 8KB IRAM
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0x0003_8000
|style="border-style: solid; border-width: 0 0 1px 0"| PRU1 8KB IRAM
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 0x0004_0000
|style="border-style: solid; border-width: 0 0 0 0"| Reserved
|}

== CFG Register Map ==
The PRUSS CFG block contains registers for control and status of power management, memory parity and enhanced PRU GP port functions.

Any register offset addresses not listed below should be considered reserved and should not be modified.

=== PRUSS_CFG Register ===
{|style="border-collapse: separate; border-spacing: 0; border-width: 1px; border-style: solid; border-color: #000; padding: 0;"
|-
!style="width: 200px; border-style: solid; border-width: 0 1px 1px 0"| Offset (Hexadecimal Bytes)
!style="width: 200px; border-style: solid; border-width: 0 1px 1px 0"| Name
!style="width: 300px; border-style: solid; border-width: 0 0 1px 0"| Description
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 0h
|style="border-style: solid; border-width: 0 1px 1px 0"| REVID
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The Revision Register, contains the ID and revision information.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 4h
|style="border-style: solid; border-width: 0 1px 1px 0"| SYSCFG
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The System Configuration Register, defines the power IDLE and STANDBY modes.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 8h
|style="border-style: solid; border-width: 0 1px 1px 0"| GPCFG0
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The General Purpose Configuration 0 Register, defines the GPI/O configuration for PRU0.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| Ch
|style="border-style: solid; border-width: 0 1px 1px 0"| GPCFG1
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The General Purpose Configuration 0 Register, defines the GPI/O configuration for PRU1.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 10h
|style="border-style: solid; border-width: 0 1px 1px 0"| CGR
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The Clock Gating Register, controls the state of Clock Management of the different modules. Software should not clear {module}_CLK_EN until {module}_CLK_STOP_ACK is 0x01.
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 14h
|style="border-style: solid; border-width: 0 1px 1px 0"| ISRP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The IRQ Status Raw Parity register is a snapshot of the IRQ raw status for the PRUSS memory parity events. The raw status is set even if the event is not enabled.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 18h
|style="border-style: solid; border-width: 0 1px 1px 0"| ISP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 18h
|style="border-style: solid; border-width: 0 1px 1px 0"| ISP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The IRQ Status Parity Register is a snapshot of the IRQ status for the PRUSS memory parity events. The status is set only if the event is enabled. Write 1 to clear the status after the interrupt has been serviced.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 1Ch
|style="border-style: solid; border-width: 0 1px 1px 0"| IESP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The IRQ Enable Set Parity Register enables the IRQ PRUSS memory parity events.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 20h
|style="border-style: solid; border-width: 0 1px 1px 0"| IECP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The IRQ Enable Clear Parity Register disables the IRQ PRUSS memory parity events.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 24h
|style="border-style: solid; border-width: 0 1px 1px 0"| SCRP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| SCR Priority Register defines the priority of some of the elements in the SCR. Lower numbers indicate higher priority level.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 28h
|style="border-style: solid; border-width: 0 1px 1px 0"| PMAO
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The PRU Master OCP Address Offset Register enables for the PRU OCP Master Port Address to have an offset of minus 0x0008_0000. This enables the PRU to access External Host address space starting at 0x00000.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 2Ch
|style="border-style: solid; border-width: 0 1px 1px 0"| MII_RT
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The MII_RT Event Enable Register enables Ethercat (or MII_RT) mode events to the PRUSS INTC.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 30h
|style="border-style: solid; border-width: 0 1px 1px 0"| IEPCLK
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The IEP Clock Source Register defines the source of the IEP clock.
|-
|style="border-style: solid; border-width: 0 1px 1px 0"| 34h
|style="border-style: solid; border-width: 0 1px 1px 0"| SPP
|style="border-style: solid; text-align: center; border-width: 0 0 1px 0"| The Scratch Pad Priority and Configuration Register defines the access priority assigned to the PRU cores and configures the scratch pad XFR shift functionality.
|-
|style="border-style: solid; border-width: 0 1px 0 0"| 40h
|style="border-style: solid; border-width: 0 1px 0 0"| PIN_MX
|style="border-style: solid; text-align: center; border-width: 0"| The Pin Mux Select Register defines the state of the PRUSS internal pinmuxing.
|}

PRUSSv2 Memory Map - Revision history

Scribe: Initial draft