Difference between revisions of "Parallella Hardware"

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==Introduction==
 
==Introduction==
[[File:BetaPopulated700x512.jpg|thumb|right|A Parallella beta board]]
+
[[File:BetaPopulated700x512.jpg|thumb|right|A Parallella Gen0 beta board]]
  
 
The key features of the Parallella board are: a Xilinz Zynq SoC which provides a Dual ARM® Cortex™-A9 processor plus programmable logic, 16 or 64-core Epiphany floating-point accelerator (32/100 GFLOPS), high bandwidth expansion via daughter cards, and interfaces that include Gigabit Ethernet, HDMI and MicroSD.
 
The key features of the Parallella board are: a Xilinz Zynq SoC which provides a Dual ARM® Cortex™-A9 processor plus programmable logic, 16 or 64-core Epiphany floating-point accelerator (32/100 GFLOPS), high bandwidth expansion via daughter cards, and interfaces that include Gigabit Ethernet, HDMI and MicroSD.
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The initial run of Parallella computers is being funded via a [http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone Kickstarter campaign], which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.
 
The initial run of Parallella computers is being funded via a [http://www.kickstarter.com/projects/adapteva/parallella-a-supercomputer-for-everyone Kickstarter campaign], which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.
  
Thanks to generous support from Xilinx the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.
+
Thanks to generous support from Xilinx, the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.
  
 
===General availability===
 
===General availability===
  
Work is being done to put distribution in place, however, a date for post-Kickstarter orders has not been confirmed yet and in the meantime interest can be registered using a form on the [http://www.parallella.org project website].
+
Parallella hardware is generally available - find a suitable supplier at http://www.parallella.org/buy/
  
 
==Revisions==
 
==Revisions==
 
[[File:ZedBoard E64G4 Wired-1024x717.jpg|thumb|right|A 66-Core Parallella Prototype]]
 
[[File:ZedBoard E64G4 Wired-1024x717.jpg|thumb|right|A 66-Core Parallella Prototype]]
  
===Prototypes===
+
===Prototype===
 +
 
 
The first Parallella prototypes shipped in late December 2012 and comprise of a [http://www.zedboard.org/ ZedBoard] plus a 16 or 64-core Epiphany FMC.  
 
The first Parallella prototypes shipped in late December 2012 and comprise of a [http://www.zedboard.org/ ZedBoard] plus a 16 or 64-core Epiphany FMC.  
  
 
From a software perspective the prototypes are virtually identical to the final form factor boards.
 
From a software perspective the prototypes are virtually identical to the final form factor boards.
  
===Beta boards===
+
===Beta (Gen0)===
 +
 
 +
The [http://www.parallella.org/2013/04/16/hello-world-my-name-is-parallella/ first 10 Parallella beta boards] came back from assembly on 11th April 2013 and were unveiled four days later at the Linux Foundation Collaboration Summit.
 +
 
 +
In July 2013 22 Gen0 boards went out Kickstarter backers, and a further 18 to key project contributors.
 +
 
 +
Backers who were due to receive a board but who opted to wait a little longer will receive a Gen1 board upgraded with a 64-core Epiphany co-processor.
 +
 
 +
===Beta (Gen1)===
 +
 
 +
Gen1 boards were manufactured in August 2013 and these were given to certain backers, key members of the community and some people who won them as prizes at the CodeMesh conference.
 +
 
 +
===Final (Gen1.1)===
 +
[[File:ParallellaGen11_700x433.jpg|thumb|right|A Parallella Gen1.1 board]]
 +
 
 +
Fixes include:
  
The [http://www.parallella.org/2013/04/16/hello-world-my-name-is-parallella/ first 10 Parallella beta boards] came back from assembly on 11th April 2013 and were unveiled four days later at the Linux Foundation Collaboration Summit.
+
* Fixed HDMI wiring issue
 +
* Made the USB port host-mode only as default build option
 +
* Removed flaky mechanical jumper for 5V mounting hole power feed
 +
* Added more ground vias for improved thermal performance
 +
* Changed Tantalum caps to ceramic caps to avoid material procurement issues
  
 
==Specifications==
 
==Specifications==
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! 66-core
 
! 66-core
 
|-
 
|-
| Target price:
+
| Price:
| US$99
+
| Starting at US$119 (Z-7010, no GPIO)
 
| US$TBC
 
| US$TBC
 
|-
 
|-
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|-
 
|-
 
| USB 2.0 ports:
 
| USB 2.0 ports:
| colspan="2" | 1x USB 2.0 | 1x USB 2.0 OTG
+
| colspan="2" | 1x USB 2.0
 
|-
 
|-
 
| Video outputs:
 
| Video outputs:
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|-
 
|-
 
| Power source:
 
| Power source:
| colspan="2" | 5 V (DC) at 1A
+
| colspan="2" | 5 V (DC) at 2A
 
|-
 
|-
 
| Size:
 
| Size:
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==Documentation==
 
==Documentation==
  
Comprehensive documentation is being made available without the need for any special access or NDAs.
+
 
  
 
===Parallella===
 
===Parallella===
  
* Preliminary [http://www.parallella.org/wp-content/uploads/2013/02/parallella_reference_4.13.2.13.pdf Parallella Reference Manual] (PDF)
+
The Parallella computer is open source hardware: the board design files are published under the Creative Commons Attribution-ShareAlike 3.0 license, and the FPGA HDL sources under the GPL.
 +
 
 +
* [http://www.parallella.org/board/ Parallella Specifications]
 +
* [https://github.com/parallella/parallella-hw/ Parallella Hardware Design] (schematics, board layout, manufacturing files, BOM and 3D models)
 
* [http://www.adapteva.com/white-papers/parallella-platform-reference-design/ Parallella Platform Reference Design] (ARM-Epiphany interface)
 
* [http://www.adapteva.com/white-papers/parallella-platform-reference-design/ Parallella Platform Reference Design] (ARM-Epiphany interface)
 
Note that the Platform Reference Design includes [https://github.com/Adapteva/parallella-platform HDL sources] that are provided under the GPL.
 
 
The Parallella board schematic and PCB layout will be published under a Creative Commons license once the release 1.0 hardware ships.
 
  
 
===Epiphany===
 
===Epiphany===
  
* [http://www.adapteva.com/support/docs/e3-reference-manual/ Epiphany Architecture Reference Manual]
+
Comprehensive documentation for the Epiphany accelerator has been made available without the need for any special access or NDAs.
 +
 
 +
* [http://www.adapteva.com/all-documents/ Epiphany Architecture Reference Manual]
 
* Epiphany-III 16-core 65nm Microprocessor (E16G301) [http://www.adapteva.com/products/silicon-devices/e16g301/  datasheet]
 
* Epiphany-III 16-core 65nm Microprocessor (E16G301) [http://www.adapteva.com/products/silicon-devices/e16g301/  datasheet]
 
* Epiphany-IV 64-core 28nm Microprocessor (E64G401) [http://www.adapteva.com/products/silicon-devices/e64g401/ datasheet]
 
* Epiphany-IV 64-core 28nm Microprocessor (E64G401) [http://www.adapteva.com/products/silicon-devices/e64g401/ datasheet]
 +
 +
{{Template:Parallella Navbox}}

Latest revision as of 15:39, 19 September 2014


Introduction

A Parallella Gen0 beta board

The key features of the Parallella board are: a Xilinz Zynq SoC which provides a Dual ARM® Cortex™-A9 processor plus programmable logic, 16 or 64-core Epiphany floating-point accelerator (32/100 GFLOPS), high bandwidth expansion via daughter cards, and interfaces that include Gigabit Ethernet, HDMI and MicroSD.

Kickstarter

The initial run of Parallella computers is being funded via a Kickstarter campaign, which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.

Thanks to generous support from Xilinx, the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.

General availability

Parallella hardware is generally available - find a suitable supplier at http://www.parallella.org/buy/

Revisions

A 66-Core Parallella Prototype

Prototype

The first Parallella prototypes shipped in late December 2012 and comprise of a ZedBoard plus a 16 or 64-core Epiphany FMC.

From a software perspective the prototypes are virtually identical to the final form factor boards.

Beta (Gen0)

The first 10 Parallella beta boards came back from assembly on 11th April 2013 and were unveiled four days later at the Linux Foundation Collaboration Summit.

In July 2013 22 Gen0 boards went out Kickstarter backers, and a further 18 to key project contributors.

Backers who were due to receive a board but who opted to wait a little longer will receive a Gen1 board upgraded with a 64-core Epiphany co-processor.

Beta (Gen1)

Gen1 boards were manufactured in August 2013 and these were given to certain backers, key members of the community and some people who won them as prizes at the CodeMesh conference.

Final (Gen1.1)

A Parallella Gen1.1 board

Fixes include:

  • Fixed HDMI wiring issue
  • Made the USB port host-mode only as default build option
  • Removed flaky mechanical jumper for 5V mounting hole power feed
  • Added more ground vias for improved thermal performance
  • Changed Tantalum caps to ceramic caps to avoid material procurement issues

Specifications

Please note that these are preliminary specifications and subject to change.

18-core 66-core
Price: Starting at US$119 (Z-7010, no GPIO) US$TBC
System-on-a-chip (SoC): Zynq 7010/7020
CPU: 800 MHz Dual ARM® Cortex™-A9 MPCore™ with CoreSight™
Many-core accelerator: Epiphany-III 16-core 65nm Microprocessor with 32 GFLOPS peak performance (E16G301) Epiphany-IV 64-core 28nm Microprocessor with 100 GFLOPS peak performance (E64G401)
Memory (SDRAM) 1024 MiB DDR3L
USB 2.0 ports: 1x USB 2.0
Video outputs: Micro HDMI
Audio outputs: Single bit SPDIF on the PEC_POWER connector
Audio inputs: none, but a USB mic or sound-card could be added
Onboard Storage: 32Mb QSPI Flash Memory | MicroSD
Onboard Network: 10/100/1000 wired Ethernet RJ45
PEC_POWER expansion: 1V, 1.35V, 1.8V, 3.3V & 5V power supplies. I2C, UART, SPDIF, JTAG
PEC_FPGA expansion: includes 48 bidirectional signals that can be configured within the Zynq device to support a number of different signal standards. When configured as LVDS signals, each differential signal pair provides a maximum bandwidth of 950Mbps. In aggregate, the PEC_FPGA connections can provide 22Gbps of total I/O bandwidth.
PEC_NORTH/PEC_SOUTH expansion: 3.2GB/s total I/O bandwidth via 2.5V LVDS 2.8GB/s total I/O bandwidth via 1.8V subLVDS
Real-time clock: None
Power source: 5 V (DC) at 2A
Size: 3.4" x 2.15"

Documentation

Parallella

The Parallella computer is open source hardware: the board design files are published under the Creative Commons Attribution-ShareAlike 3.0 license, and the FPGA HDL sources under the GPL.

Epiphany

Comprehensive documentation for the Epiphany accelerator has been made available without the need for any special access or NDAs.