The Parallella board was inspired by hardware communities such as Raspberry Pi, BeagleBoard and Arduino, and aim to democratise access to parallel computing by providing an affordable open high-performance computing (HPC) platform.
The platform is being built on the following principles:
- Open Access: all architecture and SDK documents openly published on the Web — no NDAs or special access required.
- Open Source: software platform based on free and open source software (F/OSS) development tools and libraries. Board design files provided under an open source hardware license once the Parallella computer ships.
- Affordable: the goal is to bring the hardware cost to below $100, making it an affordable platform for all.
The key features of the board are: a Xilinz Zynq SoC which provides a Dual ARM® Cortex™-A9 processor plus programmable logic, 16 or 64-core Epiphany floating-point accelerator (32/100 GFLOPS) and high bandwidth expansion via daughter cards.
The initial run of Parallella computers is being funded via a Kickstarter campaign, which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.
Thanks to generous support from Xilinx the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.
Work is being done to put distribution in place but a date for post-Kickstarter orders has not been confirmed as yet. In the meantime interest can be registered using a form on the project website.
The first Parallella prototypes shipped in late December 2012 and comprise of a ZedBoard plus a 16 or 64-core Epiphany FMC.
From a software perspective the prototypes are virtually identical to the final form factor boards.
Please note that these are preliminary specifications and subject to change.
|System-on-a-chip (SoC):||Zynq 7010/7020|
|CPU:||800 MHz Dual ARM® Cortex™-A9 MPCore™ with CoreSight™|
|Many-core accelerator:||Epiphany-III 16-core 65nm Microprocessor with 32 GFLOPS peak performance (E16G301)||Epiphany-IV 64-core 28nm Microprocessor with 100 GFLOPS peak performance (E64G401)|
|Memory (SDRAM)||1024 MiB DDR3L|
|USB 2.0 ports:||1x USB 2.0 | 1x USB 2.0 OTG|
|Video outputs:||Micro HDMI|
|Audio outputs:||Single bit SPDIF on the PEC_POWER connector|
|Audio inputs:||none, but a USB mic or sound-card could be added|
|Onboard Storage:||32Mb QSPI Flash Memory | MicroSD|
|Onboard Network:||10/100/1000 wired Ethernet RJ45|
|PEC_POWER expansion:||1V, 1.35V, 1.8V, 3.3V & 5V power supplies. I2C, UART, SPDIF, JTAG|
|PEC_FPGA expansion:||includes 48 bidirectional signals that can be configured within the Zynq device to support a number of different signal standards. When configured as LVDS signals, each differential signal pair provides a maximum bandwidth of 950Mbps. In aggregate, the PEC_FPGA connections can provide 22Gbps of total I/O bandwidth.|
|PEC_NORTH/PEC_SOUTH expansion:||3.2GB/s total I/O bandwidth via 2.5V LVDS||2.8GB/s total I/O bandwidth via 1.8V subLVDS|
|Power source:||5 V (DC) at 1A|
|Size:||3.4" x 2.15"|
For further details see the Parallella Reference Manual.