The key features of the Parallella board are: a Xilinz Zynq SoC which provides a Dual ARM® Cortex™-A9 processor plus programmable logic, 16 or 64-core Epiphany floating-point accelerator (32/100 GFLOPS), high bandwidth expansion via daughter cards, and interfaces that include Gigabit Ethernet, HDMI and MicroSD.
The initial run of Parallella computers is being funded via a Kickstarter campaign, which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.
Thanks to generous support from Xilinx the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.
Work is being done to put distribution in place, however, a date for post-Kickstarter orders has not been confirmed yet and in the meantime interest can be registered using a form on the project website.
The first Parallella prototypes shipped in late December 2012 and comprise of a ZedBoard plus a 16 or 64-core Epiphany FMC.
From a software perspective the prototypes are virtually identical to the final form factor boards.
The first 10 Parallella beta boards came back from assembly on 11th April 2013 and were unveiled four days later at the Linux Foundation Collaboration Summit.
Please note that these are preliminary specifications and subject to change.
|System-on-a-chip (SoC):||Zynq 7010/7020|
|CPU:||800 MHz Dual ARM® Cortex™-A9 MPCore™ with CoreSight™|
|Many-core accelerator:||Epiphany-III 16-core 65nm Microprocessor with 32 GFLOPS peak performance (E16G301)||Epiphany-IV 64-core 28nm Microprocessor with 100 GFLOPS peak performance (E64G401)|
|Memory (SDRAM)||1024 MiB DDR3L|
|USB 2.0 ports:||1x USB 2.0 | 1x USB 2.0 OTG|
|Video outputs:||Micro HDMI|
|Audio outputs:||Single bit SPDIF on the PEC_POWER connector|
|Audio inputs:||none, but a USB mic or sound-card could be added|
|Onboard Storage:||32Mb QSPI Flash Memory | MicroSD|
|Onboard Network:||10/100/1000 wired Ethernet RJ45|
|PEC_POWER expansion:||1V, 1.35V, 1.8V, 3.3V & 5V power supplies. I2C, UART, SPDIF, JTAG|
|PEC_FPGA expansion:||includes 48 bidirectional signals that can be configured within the Zynq device to support a number of different signal standards. When configured as LVDS signals, each differential signal pair provides a maximum bandwidth of 950Mbps. In aggregate, the PEC_FPGA connections can provide 22Gbps of total I/O bandwidth.|
|PEC_NORTH/PEC_SOUTH expansion:||3.2GB/s total I/O bandwidth via 2.5V LVDS||2.8GB/s total I/O bandwidth via 1.8V subLVDS|
|Power source:||5 V (DC) at 1A|
|Size:||3.4" x 2.15"|
Comprehensive documentation is being made available without the need for any special access or NDAs.
- Preliminary Parallella Reference Manual (PDF)
- Parallella Platform Reference Design (ARM-Epiphany interface)
- Epiphany-III 16-core 65nm Microprocessor (E16G301) datasheet
- Epiphany-IV 64-core 28nm Microprocessor (E64G401) datasheet
Note that the Platform Reference Design includes HDL sources that are provided under the GPL.
The Parallella board design will be published under a Creative Commons license once the release 1.0 hardware ships.