Difference between revisions of "Pollux"
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| − | High performance 32bit CPU Core | + | --- Technology --- |
| − | ARM926EJ- 533MHz | + | * 90 nm Process |
| − | I Cache / D Cache:16KB/16KB | + | * 288pin FBGA |
| − | Jazelle Java Hardware Accelerator | + | * 15mm x 15mm |
| − | + | * 0.65mm pitch | |
| − | DDR SDRAM Controller | + | * High performance 32bit CPU Core |
| − | 133MHz DDR SDRAM memory x 16bit | + | ** ARM926EJ- 533MHz |
| − | Single DDR memory bank | + | ** I Cache / D Cache:16KB/16KB |
| − | Up to 128MB | + | ** Jazelle Java Hardware Accelerator |
| − | + | * DDR SDRAM Controller | |
| − | Static Bus controller | + | ** 133MHz DDR SDRAM memory x 16bit |
| − | 16 bit data bus | + | ** Single DDR memory bank |
| − | Supports 8 bit NAND flash and 8/16 bit SRAM | + | ** Up to 128MB |
| − | Supports SLC/ MLC NAND | + | ** Peak Memory Bandwidth : 533MByte/sec |
| − | Boot form NAND flash or NOR flash | + | * Static Bus controller |
| − | IDE interface with PIO mode | + | *16 bit data bus |
| − | + | * Supports 8 bit NAND flash and 8/16 bit SRAM | |
| − | Display Subsystem | + | * Supports SLC/ MLC NAND |
| − | Supports screen size up to 1280 * 1024@60Hz | + | * Boot form NAND flash or NOR flash |
| − | Supports Flat Panel I/F: Color TFT at 16, 18, 24 bit//Pixel, STN-LCD | + | * IDE interface with PIO mode |
| − | Display Layers | + | * Display Subsystem |
| − | + | ** Supports screen size up to 1280 * 1024@60Hz | |
| − | + | ** Supports Flat Panel I/F: Color TFT at 16, 18, 24 bit//Pixel, STN-LCD | |
| − | Effects : Color Key, Priority, Alpha Blending(16 Levels) | + | ** Display Layers |
| − | Color Control : Brightness, Contrast, Hue, Saturation | + | *** RGB Layer : 2 Layer, 8/16/24bpp Format |
| − | Output Format | + | *** YUV Layer : YUV4:2:0, 2D/Linear Format, Scale Up/Down |
| − | + | ** Effects : Color Key, Priority, Alpha Blending(16 Levels) | |
| − | Supports NTSC/PAL Encoder with Analog DAC | + | ** Color Control : Brightness, Contrast, Hue, Saturation |
| − | + | ** Output Format | |
| − | Independent Dual Display Output | + | *** CCIR 601/656, RGB, M-RGB(Multiplexed RGB) |
| + | *** Supports NTSC/PAL Encoder with Analog DAC | ||
| + | *** CVBS Output | ||
| + | *** Independent Dual Display Output | ||
Advanced 3D Graphics | Advanced 3D Graphics | ||
Revision as of 19:47, 9 February 2010
POLLUX is the 3rd generation chip adopting MagicEyes' VRender Technology. Its high performance and low power consumption architecture realize a big differentiation in developing richer-end user applications such as 2D/3D Car Navigation System, dual display POS System, High resolution & various visual effective Display System and convergence Handheld products such as Multimedia Toy, MP4 Player, low-end PMP, and etc.
POLLUX, with its 533MHz ARM926EJ and 3D graphics engine, enables to implement high-end application such as navigation device improving from 2D graphics to 3D in progress.
POLLUX 3D graphics engine can be used not only rendering 3D contents such as 3D map but also various color LCD terminal application's needs on splendid user interface and variety of display function through its various visual effects.
POLLUX is a SoC including ARM926EJ 32bit CPU, 3D Graphics Accelerator, NTSC/PAL Encoder with video DAC and various interfaces like USB 2.0, 4ch UART, 2ch SD/MMC, I2C.
The embedded 3D Graphics engine enables high performance 3D graphics and display functions without sacrificing host CPU power to reserve most CPU power to other application software.
POLLUX provides the powerful display unit enabling simultaneous multilayer display on digital convergence system: - Displays 3 layers simultanously such as background, Cursor, 3D graphics - Enables PIP function by hardwired NTSC PAL encoder with Video DAC - Supports two difference display(1 digital & 1 analog) simultaneously
Pollux gives designers flexibility in developing system with enough CPU horse power, powerful 3D performance, multi-layering display togather with lots of I/O interfaces to realize competitiveness portable/handheld/embedded products.
--- Technology ---
- 90 nm Process
- 288pin FBGA
- 15mm x 15mm
- 0.65mm pitch
- High performance 32bit CPU Core
- ARM926EJ- 533MHz
- I Cache / D Cache:16KB/16KB
- Jazelle Java Hardware Accelerator
- DDR SDRAM Controller
- 133MHz DDR SDRAM memory x 16bit
- Single DDR memory bank
- Up to 128MB
- Peak Memory Bandwidth : 533MByte/sec
- Static Bus controller
- 16 bit data bus
- Supports 8 bit NAND flash and 8/16 bit SRAM
- Supports SLC/ MLC NAND
- Boot form NAND flash or NOR flash
- IDE interface with PIO mode
- Display Subsystem
- Supports screen size up to 1280 * 1024@60Hz
- Supports Flat Panel I/F: Color TFT at 16, 18, 24 bit//Pixel, STN-LCD
- Display Layers
- RGB Layer : 2 Layer, 8/16/24bpp Format
- YUV Layer : YUV4:2:0, 2D/Linear Format, Scale Up/Down
- Effects : Color Key, Priority, Alpha Blending(16 Levels)
- Color Control : Brightness, Contrast, Hue, Saturation
- Output Format
- CCIR 601/656, RGB, M-RGB(Multiplexed RGB)
- Supports NTSC/PAL Encoder with Analog DAC
- CVBS Output
- Independent Dual Display Output
Advanced 3D Graphics 3D Performance : 133M Texel/sec, 1.33M Polygon/sec 3D Texture Mapping, Lighting, Shading, Fogging Z-Buffer, Alpha Blending Open GL ES 1.1 support
Integrated peripherals Connectivity Interface
-USB Host/ Device(2.0), I2C, 4Ch UART, SSP/SPI
Storage Interface
-2Ch SD/MMC, NAND
Media
-I2S
User Interface, etc
-ADC, PWM
Power management modes Individual block dynamic power controller Supports various power down mode
- Idle / Stop
Operating Temperature 0℃ ~ 70℃
Operating System Microsoft Windows CE 5.0/6.0 Linux
