Difference between revisions of "R-Car/Upstream-Kernel-Release-Highlights"

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(Created page with "= Upstream Kernel Release Highlights for Renesas 32-Bit ARM and ARM64 Based SoCs = == v4.12 == Analysis Based on v4.12-rc2 === R-Car Gen3 ARM64 Based SoCs === TBD === R-C...")
 
(v4.12)
(One intermediate revision by the same user not shown)
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=== R-Car Gen3 ARM64 Based SoCs ===
 
=== R-Car Gen3 ARM64 Based SoCs ===
  
TBD
+
==== Corrections ====
 +
* r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
 +
                                                         
 +
==== Cleanups ====
 +
* Drop superfluous status update for frequency override from all r8a779[56] boards
 +
* Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
 +
* Remove unit-address and reg from integrated cache on r8a779[56] SoCs
 +
* Drop _clk suffix from X12 clock node name for r8a7795 SoC
 +
 
 +
==== Enhancements ====
 +
* Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
 +
* Add Cortex-A53 CPU cores to r8a7795 SoC
 +
* Update memory node to 4 GiB map on h3ulcb board
 +
* Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
 +
* Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
 +
* Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
 +
* Set drive-strength for ravb pins for r8a7795/salvator-x board
 +
* Enable gigabit ethernet on r8a779[56]/salvator-x boards
 +
* Enable I2C for DVFS device r8a779[56]/salvator-x boards
 +
* Add reset control properties for r8a779[56]
  
 
=== R-Car Gen2 and Gen 1, and other 32-Bit ARM Based SoCs ===
 
=== R-Car Gen2 and Gen 1, and other 32-Bit ARM Based SoCs ===
  
TBD
+
==== Corrections ====
 +
* Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
 +
* Correct Z clock for r8a7792 SoC                         
 +
* Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
 +
* Correct ethernet clock parent on r7s72100 SoC
 +
 
 +
==== Cleanups ====
 +
* Drop superfluous status update for frequency override on various boards
 +
* Always use status "okay" to enable devices on porter board
 +
* Add INTC-SYS clock to device tree of various SoCs
 +
* Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
 +
* Remove unit-address and reg from integrated cache on various SoCs
 +
* Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
 +
* Fix SCIFB0 dmas indentation on r8a774[35] SoCs
 +
* Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs
  
 +
==== Enhancements ====
 +
* Enable rtc r7s72100/genmai board
 +
* Add Z2 and DU clock for r8a7794 SoC
 +
* Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
 +
* Add reset control properties for r8a774[35] SoCs
 +
* Add watchdog timer to r7s72100 SoC
 +
* Update sdhi clock bindings on r7s72100 SoC
  
 
== v4.11 ==
 
== v4.11 ==

Revision as of 08:54, 25 May 2017

Upstream Kernel Release Highlights for Renesas 32-Bit ARM and ARM64 Based SoCs

v4.12

Analysis Based on v4.12-rc2

R-Car Gen3 ARM64 Based SoCs

Corrections

  • r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC

Cleanups

  • Drop superfluous status update for frequency override from all r8a779[56] boards
  • Tidyup Audio-DMAC channel for DVC for r8a7795 SoC
  • Remove unit-address and reg from integrated cache on r8a779[56] SoCs
  • Drop _clk suffix from X12 clock node name for r8a7795 SoC

Enhancements

  • Add all Cortex-A53 and Cortex-A57 CPU cores to r8a7796 SoC
  • Add Cortex-A53 CPU cores to r8a7795 SoC
  • Update memory node to 4 GiB map on h3ulcb board
  • Upgrade to PSCI v1.0 to support Suspend-to-RAM on r8a779[56] SoCs
  • Add SCIF1 (DEBUG1) to r8a7796/salvator-x board
  • Add all SCIF and HSCIF nodes with DMA enabled to r8a7796 SoC
  • Set drive-strength for ravb pins for r8a7795/salvator-x board
  • Enable gigabit ethernet on r8a779[56]/salvator-x boards
  • Enable I2C for DVFS device r8a779[56]/salvator-x boards
  • Add reset control properties for r8a779[56]

R-Car Gen2 and Gen 1, and other 32-Bit ARM Based SoCs

Corrections

  • Correct clock frequency of X2 DU clock input for r8a7791/koelsch board
  • Correct Z clock for r8a7792 SoC
  • Correct parent of SSI[0-9] clocks for r8a779[013] SoCs
  • Correct ethernet clock parent on r7s72100 SoC

Cleanups

  • Drop superfluous status update for frequency override on various boards
  • Always use status "okay" to enable devices on porter board
  • Add INTC-SYS clock to device tree of various SoCs
  • Tidyup Audio-DMAC channel for DVC on r8a779[013] SoCs
  • Remove unit-address and reg from integrated cache on various SoCs
  • Switch from ARCH_SHMOBILE_MULTI to ARCH_RENESAS
  • Fix SCIFB0 dmas indentation on r8a774[35] SoCs
  • Drop _clk suffix from external CAN clock node name on r8a779[01] SoCs

Enhancements

  • Enable rtc r7s72100/genmai board
  • Add Z2 and DU clock for r8a7794 SoC
  • Add power-domains to SDHI for r8a7794 and r7s72100 SoCs
  • Add reset control properties for r8a774[35] SoCs
  • Add watchdog timer to r7s72100 SoC
  • Update sdhi clock bindings on r7s72100 SoC

v4.11

R-Car Gen3 ARM64 Based SoCs

TBD

R-Car Gen2 and Gen 1, and other 32-Bit ARM Based SoCs

TBD