S3C2410

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Revision as of 17:31, 7 November 2007 by Prpplague (Talk | contribs)

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The S3C2410 is developed using an ARM920T core, 0.18um CMOS standard cells and a memory complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost and power sensitive applications. Also, the S3C2410 adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture) An outstanding feature of the S3C2410 is its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. By providing a complete set of common system peripherals, the S3C2410 minimizes overall system costs and eliminates the need to configure additional components.


To reduce total system cost, the S3C2410 also provides the following features:

  • separate 16KB Instruction and 16KB Data Cache
  • MMU to handle virtual memory management
  • LCD controller (STN & TFT)
  • NAND Flash Boot loader
  • System Manager (chip select logic, SDRAM controller)
  • 3-ch UART with handshake
  • 4-ch DMA
  • 4-ch Timers with PWM
  • I/O Ports
  • RTC
  • 8- ch 10-bit ADC and touch screen interface
  • IIC-BUS interface
  • IIS-BUS interface
  • USB Host
  • USB Device
  • SD Host & Multimedia Card Interface
  • 2-ch SPI
  • PLL for clock generation.
  • Clocked up to 203mHZ


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