Difference between revisions of "S3C2416"

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It's a [http://www.arm.com ARM926EJ] RISC '''SOC'''(System-On-Chip) made by [http://www.samsung.com/global/business/semiconductor Samsung seminconductor].<br>
 
It's a [http://www.arm.com ARM926EJ] RISC '''SOC'''(System-On-Chip) made by [http://www.samsung.com/global/business/semiconductor Samsung seminconductor].<br>
This chip is 14mm x 14mm size, FBGA package with ball pitch of 0.65mm. the S3C2416 chip is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation and Mobile Phone markets. Additionally, in order to allow for lower system costs, higher performance and low power, the S3C2416 is fabricated using the 65nm low power CMOS process.
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This chip is 14mm x 14mm size, FBGA package with ball pitch of 0.65mm. the S3C2416 chip is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation and Mobile Phone markets. Additionally, in order to allow for lower system costs, higher performance and low power, the S3C2416 is fabricated using the 65nm low power CMOS process.<br>
==Board Provider==
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All in all, the S3C2416 presents a low-cost, highly embedded solution with upgraded features.
# [http://www.techor.com/product_281.html TECHOR's] [[SOM2416|Systm-on-Module]]
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The S3C2416 carries revolutionary upgrades with respect to the S3C2412. Most notably, an upgrade to the ARM926EJ core, the integration of a 2D Graphics Accelerator, an added low power mode, as well as embedded internal ROM/RAM for secure boot, moviNAND booting and low power audio decoding. Furthermore, peripheral and feature upgrades have also been made to increase performance, as well as flexibility. Examples include a USB 1.1 host, in addition to a USB 2.0 high speed device, dual MMC ports, HSSPI ports as well as other upgraded memory interfaces.
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== Block Diagram ==
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[[File:S3c2416-BlockDiagram.jpg]]
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== Features ==
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*ARM926EJ CPU 400MHz with 16KB I-cache and 16KB D-cache
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*Dual port external memory controller: DRAM/ROM control and chip select logic
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*64KB internal general purpose SRAM
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*32KB internal ROM for moviNAND booting
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*LCD controller with DMA-dedicated: 24bpp, 2-PIP
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*2D graphics accelerator
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*6-ch DMAs with external request pins
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*4-ch UART (3Mbps) with IrDA 1.0 (64B FIFO)
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*1-ch HS-SPI (50Mbps)
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*1-ch IIC: multi-master
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*1-ch IIS: PCM and AC97 I/F
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*2-ch SD/SDIO/MMC
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*1-port USB Host v1.1 full speed
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*1-port USB Device v2.0 high speed
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*4-ch PWM timers & 1-ch internal timers
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*Real time clock & Watch dog timer
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*2 PLLs with on-chip clock generator
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*Power modes: Normal, Idle, Stop & Deep Stop, Sleep and Power-off
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*10-ch 12-bit ADC (Touch screen interface)
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*65nm low-power technology and MtCMOS technology incorporated
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*Package - 330-pins FBGA (0.65mm Pitch), 14 x 14 x 1.7mm
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==Development Board/ODM Provider==
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# [http://www.techor.com/ TECHOR's] [http://www.techor.com/product_281.html System-on-Module based on S3C2416]]([[SOM2416]])
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[[Category:ARM processors]]

Revision as of 01:42, 28 October 2011

It's a ARM926EJ RISC SOC(System-On-Chip) made by Samsung seminconductor.
This chip is 14mm x 14mm size, FBGA package with ball pitch of 0.65mm. the S3C2416 chip is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation and Mobile Phone markets. Additionally, in order to allow for lower system costs, higher performance and low power, the S3C2416 is fabricated using the 65nm low power CMOS process.
All in all, the S3C2416 presents a low-cost, highly embedded solution with upgraded features.


The S3C2416 carries revolutionary upgrades with respect to the S3C2412. Most notably, an upgrade to the ARM926EJ core, the integration of a 2D Graphics Accelerator, an added low power mode, as well as embedded internal ROM/RAM for secure boot, moviNAND booting and low power audio decoding. Furthermore, peripheral and feature upgrades have also been made to increase performance, as well as flexibility. Examples include a USB 1.1 host, in addition to a USB 2.0 high speed device, dual MMC ports, HSSPI ports as well as other upgraded memory interfaces.

Block Diagram

S3c2416-BlockDiagram.jpg


Features

  • ARM926EJ CPU 400MHz with 16KB I-cache and 16KB D-cache
  • Dual port external memory controller: DRAM/ROM control and chip select logic
  • 64KB internal general purpose SRAM
  • 32KB internal ROM for moviNAND booting
  • LCD controller with DMA-dedicated: 24bpp, 2-PIP
  • 2D graphics accelerator
  • 6-ch DMAs with external request pins
  • 4-ch UART (3Mbps) with IrDA 1.0 (64B FIFO)
  • 1-ch HS-SPI (50Mbps)
  • 1-ch IIC: multi-master
  • 1-ch IIS: PCM and AC97 I/F
  • 2-ch SD/SDIO/MMC
  • 1-port USB Host v1.1 full speed
  • 1-port USB Device v2.0 high speed
  • 4-ch PWM timers & 1-ch internal timers
  • Real time clock & Watch dog timer
  • 2 PLLs with on-chip clock generator
  • Power modes: Normal, Idle, Stop & Deep Stop, Sleep and Power-off
  • 10-ch 12-bit ADC (Touch screen interface)
  • 65nm low-power technology and MtCMOS technology incorporated
  • Package - 330-pins FBGA (0.65mm Pitch), 14 x 14 x 1.7mm


Development Board/ODM Provider

  1. TECHOR's System-on-Module based on S3C2416](SOM2416)