SparkfunCameraFPGA - Revision history

Dirk: Remove non-exiting attachment link, remove entry from wanted list

2009-05-01T08:40:17Z

Remove non-exiting attachment link, remove entry from wanted list

Glenn: catspec

2008-02-10T20:47:33Z

catspec

Glenn: +Category:Categories

2008-02-10T18:42:36Z

+Category:Categories

Wmat: Fixed links to media files

2007-09-25T13:54:25Z

Fixed links to media files

Wmat: added jpeg image

2007-09-24T20:21:58Z

added jpeg image

Wmat: Added missing page

2007-09-24T20:18:37Z

Added missing page

New page

Project by: David Carne

Structure:
* [[attachment:top.v]]
* [[attachment:capture_block.v]]
* [[attachment:freq_count.v]]
* [[attachment:cons.ucf]] - Constraint file. This will only make sense if you're deploying to a startan 3 starter kit.
* [[attachment:cam_code.psm]] - assembler source for the program rom. use picoblaze compiler.
* kcpsm3.v - NOT INCLUDED
* uart_tx.v - NOT INCLUDED
* kcuart_tx.v - NOT INCLUDED
* bbfifo_16x8.v - NOT INCLUDED
* uart_rx.v - NOT INCLUDED
* kcuart_tx.v - NOT INCLUDED
* bbfifo_16x7.v - NOT INCLUDED
* cam_code.v - NOT INCLUDED, program rom. Generated file may not be able to distribute as it contains boundary scan code under xilinx license. I'll make a stripped versiosn shortly - or just build from source file. [[attachment:cam_sources.zip source zip file]]

All the missing files can be downloaded from [http://www.xilinx.com/ipcenter/ Xilinx] picoblaze lounge. Registration and click through license are required. I'm currently working on porting the code to an open source reimplementation of the picoblaze, so you also could just wait for that to happen.

Connections:

Camera Pinout:
{| border=1
| ENB
|Y0
|-
| RST
|Y1
|-
| GND
|Y2
|-
| VCC
|Y3
|-
| SCL
|Y4
|-
| SDA
|Y5
|-
| VSYNC
|Y6
|-
| HSYNC
|Y7
|-
| VCLK
|VCC
|-
| MCLK
|GND
|}

NOTE - only valid if you use my cons.ucf on a spartan 3 starter kit [not 3e]

{| border=1
|Camera||Description||S3SK
|-
|ENB||Pullup via 1k||VCC
|-
|RST||Pullup via 1k||VCC
|-
|GND||Ground||GND
|-
|VCC||2.8V||VCC
|-
|SCL||||N/C
|-
|SDA||||N/C
|-
|VSYNC||Vertical Sync||PortB-Pin 5
|-
|HSYNC||Horizontal Sync||PortB-Pin 6
|-
|VCLK||Verticle Clock||PortB-Pin 4
|-
|MCLK||2.8V PtP 4 Mhz clock||
|-
|Y7||Data7||PortB-Pin7
|-
|Y6||Data6||PortB-Pin8
|-
|Y5||Data5||PortB-Pin9
|-
|Y4||Data4||PortB-Pin10
|-
|Y3||Data3||PortB-Pin11
|-
|Y2||Data2||PortB-Pin12
|-
|Y1||Data1||PortB-Pin13
|-
|Y0||Data0||PortB-Pin14
|}

NOTES:
* Y7 is the lsb
* Y0 is the MSB
* VCC = 2.8-3V
* VDD = 5V
* S3SK PortB Pin 1 - to GND - to increase grounding connection
* S3SK PortA Pin 1 - to GND - to increase grounding connection
* RST pull low after powerup(short to ground once at power on)
* VCC decouple with a small cap, if possible also use a ferrite bead
* MCLK needs to be a 2.8V Peak-To-Peak 4 Mhz clock - I used an avr as an oscillator and ran it through a voltage divider.
* BEFORE POWERING UP DESIGN - PROGRAM THE FPGA. Either power up while holding the prog button - and then download via jtag, or preprogram it. If you don't, some of those lines will be outputs!

Power:
If you're going to power the S3SK from a 5V bench supply, DO NOT CONNECT THE STANDARD POWER ADAPTER, and connect S3SK PortA Pin 2 to 5V. Otherwise just use the standard adapter and leave this connection off.

When all is properly connected, you'll see about 10-20ma on the 2.8v rail to the camera, and 150ma on the 5V rail to the fpga + avr.

attachment:capture.jpg

← Older revision		Revision as of 20:47, 10 February 2008
Line 120:		Line 120:
	[[Image:Capture.jpg]]		[[Image:Capture.jpg]]

−	[[Category:~~Categories~~]]	+	[[Category:Hardware]]

← Older revision		Revision as of 18:42, 10 February 2008
Line 119:		Line 119:

	[[Image:Capture.jpg]]		[[Image:Capture.jpg]]
		+
		+	[[Category:Categories]]

← Older revision		Revision as of 20:21, 24 September 2007
Line 118:		Line 118:


−	~~attachment~~:~~capture~~.jpg	+	[[Image:Capture.jpg]]

@@ Line 14: / Line 14: @@
   * kcuart_tx.v - NOT INCLUDED
   * bbfifo_16x7.v - NOT INCLUDED
-  * cam_code.v - NOT INCLUDED, program rom. Generated file may not be able to distribute as it contains boundary scan code under xilinx license. I'll make a stripped versiosn shortly - or just build from source file. [[attachment:cam_sources.zip source zip file]]
+  * cam_code.v - NOT INCLUDED, program rom. Generated file may not be able to distribute as it contains boundary scan code under xilinx license. I'll make a stripped versiosn shortly - or just build from source file.

@@ Line 1: / Line 1: @@
 Project by: David Carne
-Structure:
+==Structure==
-  * [[attachment:top.v]]
+  * [[Media:Top.v|Top.v]]
-  * [[attachment:capture_block.v]]
+  * [[Media:capture_block.v|capture_block.v]]
-  * [[attachment:freq_count.v]]
+  * [[Media:freq_count.v|freq_count.v]]
-  * [[attachment:cons.ucf]] - Constraint file. This will only make sense if you're deploying to a startan 3 starter kit.
+  * [[Media:cons.ucf|cons.ucf]] - Constraint file. This will only make sense if you're deploying to a startan 3 starter kit.
-  * [[attachment:cam_code.psm]] - assembler source for the program rom. use picoblaze compiler.
+  * [[Media:cam_code.psm|cam_code.psm]] - assembler source for the program rom. use picoblaze compiler.
   * kcpsm3.v - NOT INCLUDED
   * uart_tx.v - NOT INCLUDED