Difference between revisions of "SpiSlaveZero"

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(Register Read/Write Cycles)
(SPI Slave Zero)
 
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SPI Slave Zero is a specification for SPI peripheral intended for verification of SPI master drivers. The concept is borrowed from that of USB Gadget Zero which serves as a test endpoint for USB HCI drivers. The intention of the specification is to be broad enough to be implemented on a wide range of microcontrollers and SoCs with capable hardware SPI slave peripherals or optionally via bitbanging.
 
SPI Slave Zero is a specification for SPI peripheral intended for verification of SPI master drivers. The concept is borrowed from that of USB Gadget Zero which serves as a test endpoint for USB HCI drivers. The intention of the specification is to be broad enough to be implemented on a wide range of microcontrollers and SoCs with capable hardware SPI slave peripherals or optionally via bitbanging.
  
=== SSZ Specification Rev 0.1 ===
+
=== SSZ Specification Rev 0.1 DRAFT ===
  
 
SPI Slave Zero (SSZ) is a SPI peripheral supporting streaming read of a data test pattern, write sinking, and optionally write storage and read back for data integrity testing. The peripheral supports a combination of out-of-band signals to control reset and fundamental protocol configuration as well as a register set for driver discovery of supported features for a given implementation.
 
SPI Slave Zero (SSZ) is a SPI peripheral supporting streaming read of a data test pattern, write sinking, and optionally write storage and read back for data integrity testing. The peripheral supports a combination of out-of-band signals to control reset and fundamental protocol configuration as well as a register set for driver discovery of supported features for a given implementation.
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* RESETn
 
* RESETn
 
* MODE[1..0]
 
* MODE[1..0]
 +
* R/W
  
 
==== Initialization ====
 
==== Initialization ====
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A register cycle consists of an address word being written to select an internal register. This is followed by a second word that is read/written in order to read/write the 8-bit register contents.
 
A register cycle consists of an address word being written to select an internal register. This is followed by a second word that is read/written in order to read/write the 8-bit register contents.
  
<Insert timing diagram here>
+
* describe chip select and R/W behavior
 +
* Insert timing diagram here
  
==== Command Protocol ====
+
==== Registers ====
 +
 
 +
=====  Version (0x00) =====
 +
 
 +
7 6 5 4 3 2 1 0
 +
M M M M N N N N
 +
 
 +
MMMM and NNNN are BCD encoded digits of the SSZ implementation version. For 0.1 this corresponds to 00000001
 +
 
 +
===== Clock Rate High (0x01) =====
 +
 
 +
7 6 5 4 3 2 1 0
 +
H H H H H H H H
  
 
TBD
 
TBD
  
==== Register 0x00 ====
+
===== Clock Rate Low (0x02) =====
 +
 
 +
7 6 5 4 3 2 1 0
 +
L L L L L L L L
  
 
TBD
 
TBD

Latest revision as of 15:52, 21 February 2013

SPI Slave Zero

SPI Slave Zero is a specification for SPI peripheral intended for verification of SPI master drivers. The concept is borrowed from that of USB Gadget Zero which serves as a test endpoint for USB HCI drivers. The intention of the specification is to be broad enough to be implemented on a wide range of microcontrollers and SoCs with capable hardware SPI slave peripherals or optionally via bitbanging.

SSZ Specification Rev 0.1 DRAFT

SPI Slave Zero (SSZ) is a SPI peripheral supporting streaming read of a data test pattern, write sinking, and optionally write storage and read back for data integrity testing. The peripheral supports a combination of out-of-band signals to control reset and fundamental protocol configuration as well as a register set for driver discovery of supported features for a given implementation.

I/O Resources

SSZ requires the following minimal signal resources:

  • MOSI
  • MISO
  • SCLK
  • SS
  • RESETn
  • MODE[1..0]
  • R/W

Initialization

Exact steps:

  • RESETn is asserted by the master for 10ms.
  • MODE[1..0] is asserted with the SPI clock polarity/phase mode (encoded as MODE[1]==CPOL and MODE[0]==CPHA)
  • RESETn is deasserted

Once initialized, the SSZ device will operate using the polarity/phase mode sampled when RESETn is deasserted. All internal registers will be reset to their defaults after RESETn is deasserted.

Clocking

After initialization, the maximum clock rate of the SSZ device is unknown by the SPI master. The master shall initially drive SCLK at a frequency of no more than 100 KHz. This allows SSZ to be implemented in a wide range of hardware. Discovery of the actual max SSZ implementation frequency can be performed by reading an internal SSZ register.

Register Read/Write Protocol

Internal registers are accessed only in 8-bit word mode. Register addresses are 8-bits and each register is 8-bits in size.

A register cycle consists of an address word being written to select an internal register. This is followed by a second word that is read/written in order to read/write the 8-bit register contents.

  • describe chip select and R/W behavior
  • Insert timing diagram here

Registers

Version (0x00)
7 6 5 4 3 2 1 0
M M M M N N N N

MMMM and NNNN are BCD encoded digits of the SSZ implementation version. For 0.1 this corresponds to 00000001

Clock Rate High (0x01)
7 6 5 4 3 2 1 0
H H H H H H H H

TBD

Clock Rate Low (0x02)
7 6 5 4 3 2 1 0
L L L L L L L L

TBD