Difference between revisions of "Ti AM33XX PRUSSv2"

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== Available PRU Resources ==
 
== Available PRU Resources ==
 +
[[File:PRUSS.png|AM335x PRUSS]]
 +
 
[[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]
 
[[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]
  
Line 33: Line 35:
 
: One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.
 
: One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.
  
; [http://en.wikipedia.org/wiki/Open_Core_Protocol| Open Core Protocol] (OCP) master port
+
; [http://en.wikipedia.org/wiki/Open_Core_Protocol Open Core Protocol] (OCP) master port
 
: Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.
 
: Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.
  
Line 70: Line 72:
 
[[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]
 
[[PRUSSv2 Interrupts| Click here for a full list of PRUSS Interrupts.]]
  
The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace.
+
The current [https://github.com/beagleboard/am335x_pru_package/blob/master/pru_sw/app_loader/interface/prussdrv.c example PRU loader] uses [http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=f1a304e7941cc76353363a139cbb6a4b1ca7c737 UIO], but this ideally should be replaced with [http://omappedia.org/wiki/Category:RPMsg remoteproc] rather than poking at the registers from userspace. In the mean time, according to [https://groups.google.com/d/msg/beagleboard/gqCjxh4uZi0/_uIUD8ZF88QJ this discussion:] we can use the included script and load the uio_pruss userspace driver.
  
 
=== PRU to Host (PRU to ARM Cortex-A8) ===
 
=== PRU to Host (PRU to ARM Cortex-A8) ===
 +
Include the uio_pruss kernel driver by using '''modprobe uio_pruss''' or the steps outlined above, if that does not work.
 +
Then in a project include the header files for the am335x_pru_package.
  
 +
    #define PRU_NUM0   0
 +
    // Driver header file
 +
    #include <prussdrv.h>
 +
    #include <pruss_intc_mapping.h>
  
 +
/* Then, initialize the interrupt controller data */
 +
    tpruss_intc_initdata pruss_intc_initdata = PRUSS_INTC_INITDATA;
 +
/* Initialize the PRU */
 +
    prussdrv_init ();
 +
/* Get the interrupt initialized */
 +
    prussdrv_pruintc_init(&pruss_intc_initdata)
  
 +
/* Execute example on PRU0 where first argument is the PRU# and second is the assembly to execute*/
 +
    prussdrv_exec_program (PRU_NUM0, "./example.bin");
 +
 +
/* Wait until PRU0 sends the interrupt*/
 +
    prussdrv_pru_wait_event (PRU_EVTOUT_0);
 +
/* Clear the interrupt*/
 +
    prussdrv_pru_clear_event (PRU0_ARM_INTERRUPT);
 +
 +
The PRU (in this case 0) will have the following in the example.bin file to trigger the interrupt:
 +
    #define PRU0_ARM_INTERRUPT      19
 +
    MOV      r31.b0, PRU0_ARM_INTERRUPT+16
 +
 +
Register 31 allows for control of the INTC for the PRU.
  
 
=== Host to PRU (ARM Cortex-A8 to PRU) ===
 
=== Host to PRU (ARM Cortex-A8 to PRU) ===
Line 97: Line 124:
 
|-
 
|-
 
|'''PRU #'''
 
|'''PRU #'''
|'''R30(input) bit'''
+
|'''R30(output) bit'''
 
|'''Pinmux Mode'''
 
|'''Pinmux Mode'''
|'''R31(output) bit'''
+
|'''R31(input) bit'''
 
|'''Pinmux Mode'''
 
|'''Pinmux Mode'''
 
|'''BB Header'''
 
|'''BB Header'''
Line 110: Line 137:
 
|-
 
|-
 
|0
 
|0
 +
|0
 +
|Mode_5
 
|0
 
|0
 
|Mode_6
 
|Mode_6
|0
 
|Mode_5
 
 
|P9_31
 
|P9_31
 
|SPI1_SCLK
 
|SPI1_SCLK
Line 123: Line 150:
 
|-
 
|-
 
|0
 
|0
 +
|1
 +
|Mode_5
 
|1
 
|1
 
|Mode_6
 
|Mode_6
|1
+
|P9_29
|Mode_5
 
|P9_31
 
 
|SPI1_D0
 
|SPI1_D0
 
|mcasp0_fsx
 
|mcasp0_fsx
Line 136: Line 163:
 
|-
 
|-
 
|0
 
|0
 +
|2
 +
|Mode_5
 
|2
 
|2
 
|Mode_6
 
|Mode_6
|2
 
|Mode_5
 
 
|P9_30
 
|P9_30
 
|SPI1_D1
 
|SPI1_D1
Line 149: Line 176:
 
|-
 
|-
 
|0
 
|0
 +
|3
 +
|Mode_5
 
|3
 
|3
 
|Mode_6
 
|Mode_6
|3
 
|Mode_5
 
 
|P9_28
 
|P9_28
 
|SPI1_CS0
 
|SPI1_CS0
Line 162: Line 189:
 
|-
 
|-
 
|0
 
|0
 +
|4
 +
|Mode_5
 
|4
 
|4
 
|Mode_6
 
|Mode_6
|4
 
|Mode_5
 
 
|P9_42
 
|P9_42
|(*see note1 below)
+
|<span style="color: red">(*note1)</span>
 
|mcasp0_aclkr
 
|mcasp0_aclkr
 
|9A0h
 
|9A0h
Line 175: Line 202:
 
|-
 
|-
 
|0
 
|0
 +
|5
 +
|Mode_5
 
|5
 
|5
 
|Mode_6
 
|Mode_6
|5
 
|Mode_5
 
 
|P9_27
 
|P9_27
 
|GPIO3_19
 
|GPIO3_19
Line 188: Line 215:
 
|-
 
|-
 
|0
 
|0
 +
|6
 +
|Mode_5
 
|6
 
|6
 
|Mode_6
 
|Mode_6
|6
 
|Mode_5
 
 
|P9_41
 
|P9_41
|(*see note2 below)
+
|<span style="color: red">(*note2)</span>
 
|mcasp0_axr1
 
|mcasp0_axr1
 
|9A8h
 
|9A8h
Line 201: Line 228:
 
|-
 
|-
 
|0
 
|0
 +
|7
 +
|Mode_5
 
|7
 
|7
 
|Mode_6
 
|Mode_6
|7
 
|Mode_5
 
 
|P9_25
 
|P9_25
 
|GPIO3_21
 
|GPIO3_21
Line 214: Line 241:
 
|-
 
|-
 
|0
 
|0
 +
|14
 +
|Mode_6
 
|N/A
 
|N/A
 
|
 
|
|14
 
|Mode_6
 
 
|P8_12
 
|P8_12
 
|GPIO1_12
 
|GPIO1_12
Line 223: Line 250:
 
|830h
 
|830h
 
|0x030
 
|0x030
|NA
+
|N/A
 
|0x25
 
|0x25
 
|-
 
|-
 
|0
 
|0
 +
|15
 +
|Mode_6
 
|N/A
 
|N/A
 
|
 
|
|15
 
|Mode_6
 
 
|P8_11
 
|P8_11
 
|GPIO1_13
 
|GPIO1_13
|gpmc_ad9
+
|gpmc_ad13
|824h
+
|834h
|0x024
+
|0x034
|NA
+
|N/A
 
|0x25
 
|0x25
 
|-
 
|-
 
|0
 
|0
 +
|N/A
 +
|
 
|14
 
|14
 
|Mode_6
 
|Mode_6
|N/A
 
|
 
 
|P8_16
 
|P8_16
 
|GPIO1_14
 
|GPIO1_14
Line 250: Line 277:
 
|0x038
 
|0x038
 
|0x06
 
|0x06
|NA
+
|N/A
 
|-
 
|-
 
|0
 
|0
 +
|N/A
 +
|
 
|15
 
|15
 
|Mode_6
 
|Mode_6
|N/A
 
|
 
 
|P8_15
 
|P8_15
 
|GPIO1_15
 
|GPIO1_15
Line 263: Line 290:
 
|0x03C
 
|0x03C
 
|0x06
 
|0x06
|NA
+
|N/A
 
|-
 
|-
 
|0
 
|0
 +
|N/A
 +
|
 
|16
 
|16
 
|Mode_6
 
|Mode_6
|N/A
 
|
 
 
|P9_24
 
|P9_24
 
|UART1_TXD
 
|UART1_TXD
Line 276: Line 303:
 
|0x184
 
|0x184
 
|0x06
 
|0x06
|NA
+
|N/A
 
|-
 
|-
 
|1
 
|1
 +
|0
 +
|Mode_5
 
|0
 
|0
 
|Mode_6
 
|Mode_6
|0
 
|Mode_5
 
 
|P8_45
 
|P8_45
 
|GPIO2_6
 
|GPIO2_6
Line 292: Line 319:
 
|-
 
|-
 
|1
 
|1
 +
|1
 +
|Mode_5
 
|1
 
|1
 
|Mode_6
 
|Mode_6
|1
 
|Mode_5
 
 
|P8_46
 
|P8_46
 
|GPIO2_7
 
|GPIO2_7
Line 305: Line 332:
 
|-
 
|-
 
|1
 
|1
 +
|2
 +
|Mode_5
 
|2
 
|2
 
|Mode_6
 
|Mode_6
|2
 
|Mode_5
 
 
|P8_43
 
|P8_43
 
|GPIO2_8
 
|GPIO2_8
Line 318: Line 345:
 
|-
 
|-
 
|1
 
|1
 +
|3
 +
|Mode_5
 
|3
 
|3
 
|Mode_6
 
|Mode_6
|3
 
|Mode_5
 
 
|P8_44
 
|P8_44
 
|GPIO2_9
 
|GPIO2_9
Line 331: Line 358:
 
|-
 
|-
 
|1
 
|1
 +
|4
 +
|Mode_5
 
|4
 
|4
 
|Mode_6
 
|Mode_6
|4
 
|Mode_5
 
 
|P8_41
 
|P8_41
 
|GPIO2_10
 
|GPIO2_10
Line 344: Line 371:
 
|-
 
|-
 
|1
 
|1
 +
|5
 +
|Mode_5
 
|5
 
|5
 
|Mode_6
 
|Mode_6
|5
 
|Mode_5
 
 
|P8_42
 
|P8_42
 
|GPIO2_11
 
|GPIO2_11
Line 357: Line 384:
 
|-
 
|-
 
|1
 
|1
 +
|6
 +
|Mode_5
 
|6
 
|6
 
|Mode_6
 
|Mode_6
|6
 
|Mode_5
 
 
|P8_39
 
|P8_39
 
|GPIO2_12
 
|GPIO2_12
Line 370: Line 397:
 
|-
 
|-
 
|1
 
|1
 +
|7
 +
|Mode_5
 
|7
 
|7
 
|Mode_6
 
|Mode_6
|7
 
|Mode_5
 
 
|P8_40
 
|P8_40
 
|GPIO2_13
 
|GPIO2_13
Line 383: Line 410:
 
|-
 
|-
 
|1
 
|1
 +
|8
 +
|Mode_5
 
|8
 
|8
 
|Mode_6
 
|Mode_6
|8
 
|Mode_5
 
 
|P8_27
 
|P8_27
 
|GPIO2_22
 
|GPIO2_22
Line 396: Line 423:
 
|-
 
|-
 
|1
 
|1
 +
|9
 +
|Mode_5
 
|9
 
|9
 
|Mode_6
 
|Mode_6
|9
 
|Mode_5
 
 
|P8_29
 
|P8_29
 
|GPIO2_23
 
|GPIO2_23
Line 409: Line 436:
 
|-
 
|-
 
|1
 
|1
 +
|10
 +
|Mode_5
 
|10
 
|10
 
|Mode_6
 
|Mode_6
|10
 
|Mode_5
 
 
|P8_28
 
|P8_28
 
|GPIO2_24
 
|GPIO2_24
Line 422: Line 449:
 
|-
 
|-
 
|1
 
|1
 +
|11
 +
|Mode_5
 
|11
 
|11
 
|Mode_6
 
|Mode_6
|11
 
|Mode_5
 
 
|P8_30
 
|P8_30
 
|GPIO2_25
 
|GPIO2_25
Line 435: Line 462:
 
|-
 
|-
 
|1
 
|1
 +
|12
 +
|Mode_5
 
|12
 
|12
 
|Mode_6
 
|Mode_6
|12
 
|Mode_5
 
 
|P8_21
 
|P8_21
 
|GPIO1_30
 
|GPIO1_30
Line 448: Line 475:
 
|-
 
|-
 
|1
 
|1
 +
|13
 +
|Mode_5
 
|13
 
|13
 
|Mode_6
 
|Mode_6
|13
 
|Mode_5
 
 
|P8_20
 
|P8_20
 
|GPIO1_31
 
|GPIO1_31
Line 461: Line 488:
 
|-
 
|-
 
|1
 
|1
 +
|N/A
 +
|
 
|16
 
|16
 
|Mode_6
 
|Mode_6
|N/A
 
|
 
 
|P9_26
 
|P9_26
 
|UART1_RXD
 
|UART1_RXD
Line 474: Line 501:
 
|-
 
|-
 
|}
 
|}
 
+
<pre style="color: red">
 
*Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin.  You MUST set GPIO0_7 to input mode in pinmuxing.
 
*Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin.  You MUST set GPIO0_7 to input mode in pinmuxing.
  
 
*Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.
 
*Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.
 +
</pre>
 +
 +
== Assembly ==
 +
The complete list of PRU assembly instructions can be found [http://processors.wiki.ti.com/index.php/PRU_Assembly_Instructions at TI].
 +
=== Four instruction classes ===
 +
* Arithmetic
 +
* Logical
 +
* Flow Control
 +
* Register Load/Store
 +
 +
=== Instruction Syntax ===
 +
* Mnemonic, followed by comma separated parameter list
 +
* Parameters can be a register, label, immediate value, or constant table entry
 +
* Example
 +
** SUB r3, r4, 10
 +
** Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)
  
 
== Resources ==
 
== Resources ==
 +
* [https://groups.google.com/forum/?fromgroups#!topic/beagleboard/u28ytaoNenU PRU FAQ]
 
* [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]
 
* [https://github.com/beagleboard/am335x_pru_package AM335x PRU support package on Github]
 
* [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]
 
* [https://github.com/beagleboard/am335x_pru_package/blob/master/am335xPruReferenceGuide.pdf?raw=true AM335x PRU-ICSS Reference Guide]
The documentation on the subsystem is  [[media:spruh73c.pdf|here]].  TI does not support this subsystem and all questions/inquires/problems should be directed to the community.
+
* The documentation on the subsystem is  [[media:spruh73c.pdf|here]].  TI does not support this subsystem and all questions/inquires/problems should be directed to the community.
 +
* Example for the first PRU version (Ti AM18XX  and other DSP) [http://www.ti.com/tool/sprc940 http://www.ti.com/tool/sprc940]
 +
* [http://www.element14.com/community/community/knode/single-board_computers/next-gen_beaglebone/blog/2013/05/22/bbb--working-with-the-pru-icssprussv2 Element14 write-up on using PRU]
  
 
* [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]
 
* [https://github.com/sagedevices/ti-pruv2-assembly-textmate-bundle PRU assembly syntax highlighting for TextMate, Sublime Text, etc.]
 +
 +
* A userspace [https://docs.google.com/file/d/0B80aJokrBccAV1paMTU0bjM1OXc/edit?usp=sharing debugging utility] with credit to PRU_EVTOUT_2 from the #beagle IRC channel.
 +
* ncurses based debugger work has started at [https://github.com/wz2b/prude here].
 +
* A classic CLI debugger is available on SourceForge called [http://sourceforge.net/projects/prudebug prudebug].
 +
* For using the Open Core Protocol to [http://nomel.org/post/30006622413/beaglebone-tutorial-accessing-main-memory-from-the-pru access external memory] from the PRU.
  
 
== Examples ==
 
== Examples ==
Line 491: Line 542:
 
* [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]
 
* [https://github.com/mranostay/beagle-nixie BeagleBone Nixie Cape PRU App]
 
* [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]
 
* [http://processors.wiki.ti.com/index.php/Soft-UART_Implementation_on_AM335X_PRU_-_Software_Users_Guide PRU Soft UART Driver]
 +
 +
[[Category:ECE497 | PRU]]

Revision as of 23:18, 1 September 2013

The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O. These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.

PRUs are programmed in Assembly, with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.

This is a Work In Progress

Available PRU Resources

AM335x PRUSS

Click here for a full list of register mappings.

Per PRU

8KB program memory
Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.
Enhanced GPIO (EGPIO)
High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.
PRU0
pr1_pru_0_pru_r30[15:0] (PRU0 Register R30 Outputs)
pr1_pru_0_pru_r31[16:0] (PRU0 Register R31 Inputs)
PRU1
pr1_pru_1_pru_r30[15:0] (PRU1 Register R30 Outputs)
pr1_pru_1_pru_r31[16:0] (PRU1 Register R31 Inputs)
Hardware capture modes
Serial 28-bit shift in and out.
Parallel 16-bit capture on clock.
MII standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).
A 32-bit multiply and accumulate unit (MAC)
Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).
8KB data memory
Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.
One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.
Open Core Protocol (OCP) master port
Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.

Shared Between PRUs

Scratch pad
3 banks of 30 32-bit registers (total 90 32-bit registers).
Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.
12KB data memory
Accessed over the 32-but bus, not single-cycle.

Local Peripherals

Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.

Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.

Enhanced Capture Model (eCAP)
Industrial Ethernet Peripheral (IEP)
Universal Asynchronous Receiver/Transmitter (UART0)
Used to perform serial data transmission to the TL16C550 industry standard.
16-bit FIFO receive and transmit buffers + per byte error status.
Can generate Interrupt requests for the PRUSS Interrupt Controller.
Can generate DMA requests for the EDMA SoC DMA controller.
Maximum transmission speed of 192MHz (192Mbps - 24MB/s).

Communication

Communication between various elements of the PRUSS or the wider SoC may take place either directly, over a bus, via interrupts or via DMA.

The following lists will expose all possible communication approaches for each likely scenario.

For communication via interrupts, please first read the section on the PRUSSv2 Interrupt Controller.

Click here for a full list of PRUSS Interrupts.

The current example PRU loader uses UIO, but this ideally should be replaced with remoteproc rather than poking at the registers from userspace. In the mean time, according to this discussion: we can use the included script and load the uio_pruss userspace driver.

PRU to Host (PRU to ARM Cortex-A8)

Include the uio_pruss kernel driver by using modprobe uio_pruss or the steps outlined above, if that does not work. Then in a project include the header files for the am335x_pru_package.

   #define PRU_NUM0	  0
   // Driver header file
   #include <prussdrv.h>
   #include <pruss_intc_mapping.h>	 

/* Then, initialize the interrupt controller data */

   tpruss_intc_initdata pruss_intc_initdata = PRUSS_INTC_INITDATA;

/* Initialize the PRU */

   prussdrv_init ();

/* Get the interrupt initialized */

   prussdrv_pruintc_init(&pruss_intc_initdata)

/* Execute example on PRU0 where first argument is the PRU# and second is the assembly to execute*/

   prussdrv_exec_program (PRU_NUM0, "./example.bin");

/* Wait until PRU0 sends the interrupt*/

   prussdrv_pru_wait_event (PRU_EVTOUT_0);

/* Clear the interrupt*/

   prussdrv_pru_clear_event (PRU0_ARM_INTERRUPT);

The PRU (in this case 0) will have the following in the example.bin file to trigger the interrupt:

   #define PRU0_ARM_INTERRUPT      19
   MOV       r31.b0, PRU0_ARM_INTERRUPT+16

Register 31 allows for control of the INTC for the PRU.

Host to PRU (ARM Cortex-A8 to PRU)

Interrupts

Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively. By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.

To configure


PRU to external peripherals

External peripherals to PRU

PRU to internal peripherals

Internal peripherals to PRU

Loading a PRU Program

Beaglebone PRU connections and modes

PRU # R30(output) bit Pinmux Mode R31(input) bit Pinmux Mode BB Header BB Pin Name ZCZ BallName Offset Reg DT Offset Input Mode Output Mode
0 0 Mode_5 0 Mode_6 P9_31 SPI1_SCLK mcasp0_aclkx 990h 0x190 0x06 0x25
0 1 Mode_5 1 Mode_6 P9_29 SPI1_D0 mcasp0_fsx 994h 0x194 0x06 0x25
0 2 Mode_5 2 Mode_6 P9_30 SPI1_D1 mcasp0_axr0 998h 0x198 0x06 0x25
0 3 Mode_5 3 Mode_6 P9_28 SPI1_CS0 mcasp0_ahclkr 99Ch 0x19C 0x06 0x25
0 4 Mode_5 4 Mode_6 P9_42 (*note1) mcasp0_aclkr 9A0h 0x1A0 0x06 0x25
0 5 Mode_5 5 Mode_6 P9_27 GPIO3_19 mcasp0_fsr 9A4h 0x1A4 0x06 0x25
0 6 Mode_5 6 Mode_6 P9_41 (*note2) mcasp0_axr1 9A8h 0x1A8 0x06 0x25
0 7 Mode_5 7 Mode_6 P9_25 GPIO3_21 mcasp0_ahclkx 9ACh 0x1AC 0x06 0x25
0 14 Mode_6 N/A P8_12 GPIO1_12 gpmc_ad12 830h 0x030 N/A 0x25
0 15 Mode_6 N/A P8_11 GPIO1_13 gpmc_ad13 834h 0x034 N/A 0x25
0 N/A 14 Mode_6 P8_16 GPIO1_14 gpmc_ad14 838h 0x038 0x06 N/A
0 N/A 15 Mode_6 P8_15 GPIO1_15 gpmc_ad15 83Ch 0x03C 0x06 N/A
0 N/A 16 Mode_6 P9_24 UART1_TXD uart1_txd 984h 0x184 0x06 N/A
1 0 Mode_5 0 Mode_6 P8_45 GPIO2_6 lcd_data0 8A0h 0x0A0 0x06 0x25
1 1 Mode_5 1 Mode_6 P8_46 GPIO2_7 lcd_data1 8A4h 0x0A4 0x06 0x25
1 2 Mode_5 2 Mode_6 P8_43 GPIO2_8 lcd_data2 8A8h 0x0A8 0x06 0x25
1 3 Mode_5 3 Mode_6 P8_44 GPIO2_9 lcd_data3 8ACh 0x0AC 0x06 0x25
1 4 Mode_5 4 Mode_6 P8_41 GPIO2_10 lcd_data4 8B0h 0x0B0 0x06 0x25
1 5 Mode_5 5 Mode_6 P8_42 GPIO2_11 lcd_data5 8B4h 0x0B4 0x06 0x25
1 6 Mode_5 6 Mode_6 P8_39 GPIO2_12 lcd_data6 8B8h 0x0B8 0x06 0x25
1 7 Mode_5 7 Mode_6 P8_40 GPIO2_13 lcd_data7 8BCh 0x0BC 0x06 0x25
1 8 Mode_5 8 Mode_6 P8_27 GPIO2_22 lcd_vsync 8E0h 0x0EO 0x06 0x25
1 9 Mode_5 9 Mode_6 P8_29 GPIO2_23 lcd_hsync 8E4h 0x0E4 0x06 0x25
1 10 Mode_5 10 Mode_6 P8_28 GPIO2_24 lcd_pclk 8E8h 0x0E8 0x06 0x25
1 11 Mode_5 11 Mode_6 P8_30 GPIO2_25 lcd_ac_bias_en 8ECh 0x0EC 0x06 0x25
1 12 Mode_5 12 Mode_6 P8_21 GPIO1_30 gpmc_csn1 880h 0x080 0x06 0x25
1 13 Mode_5 13 Mode_6 P8_20 GPIO1_31 gpmc_csn2 884h 0x084 0x06 0x25
1 N/A 16 Mode_6 P9_26 UART1_RXD uart1_rxd 980h 0x180 0x06 NA
*Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin.  You MUST set GPIO0_7 to input mode in pinmuxing.

*Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.

Assembly

The complete list of PRU assembly instructions can be found at TI.

Four instruction classes

  • Arithmetic
  • Logical
  • Flow Control
  • Register Load/Store

Instruction Syntax

  • Mnemonic, followed by comma separated parameter list
  • Parameters can be a register, label, immediate value, or constant table entry
  • Example
    • SUB r3, r4, 10
    • Subtracts immediate value 10 (decimal) from the value in r4 and then places the result in r3 (or r3 = r4 - 10)

Resources

  • A userspace debugging utility with credit to PRU_EVTOUT_2 from the #beagle IRC channel.
  • ncurses based debugger work has started at here.
  • A classic CLI debugger is available on SourceForge called prudebug.
  • For using the Open Core Protocol to access external memory from the PRU.

Examples