Ti AM33XX PRUSSv2
The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O. These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.
PRUs are programmed in Assembly, with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200Mhz, a single cycle will always take 5ns (nanoseconds) to execute.
This is a Work In Progress
Available PRU Resources
- 8KB program memory
- Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.
- Enhanced GPIO (EGPIO)
- High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.
- pr1_pru_0_pru_r30[15:0] (PRU0 Register R30 Outputs)
- pr1_pru_0_pru_r31[16:0] (PRU0 Register R31 Inputs)
- pr1_pru_1_pru_r30[15:0] (PRU1 Register R30 Outputs)
- pr1_pru_1_pru_r31[16:0] (PRU1 Register R31 Inputs)
- Hardware capture modes
- Serial 28-bit shift in and out.
- Parallel 16-bit capture on clock.
- MII standardised capture mode, used for implementing media independent Fast Ethernet (100Mbps - 25MHz 4-bit).
- A 32-bit multiply and accumulate unit (MAC)
- Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).
- 8KB data memory
- Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.
- One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.
- Open Core Protocol (OCP) master port
- Access to the data bus that interconnects all peripherals on the SoC, including the ARM Cortex-A8, used for data transfer directly to and from the PRU in Level 3 (L3) memory space.
- Scratch pad
- 3 banks of 30 32-bit registers (total 90 32-bit registers).
- Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.
- 12KB data memory
- Accessed over the 32-but bus, not single-cycle.
Local peripherals are those present within the PRUSS and not those belonging to the entire SoC. Peripherals are accessed from PRUs over the Switched Central Resource (SCR) 32-bit bus within the PRUSS.
Attached to the SCR bus is also an OCP slave, enabling OCP masters from outside of the PRUSS to access these local peripherals in Level 4 (L4) memory space.
- Enhanced Capture Model (eCAP)
- Industrial Ethernet Peripheral (IEP)
- Universal Asynchronous Receiver/Transmitter (UART0)
- Used to perform serial data transmission to the TL16C550 industry standard.
- 16-bit FIFO receive and transmit buffers + per byte error status.
- Can generate Interrupt requests for the PRUSS Interrupt Controller.
- Can generate DMA requests for the EDMA SoC DMA controller.
- Maximum transmission speed of 192MHz (192Mbps - 24MB/s).