Tims USB Notes

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Here is a bunch of miscellaneous information about USB in Linux:

controller IP suppliers

  • Synopsys - DesignWare - DWC3 Used on Qualcomm, Exynos and Omap SoCs; DWC2 used on Rockchip SoCs
  • Chipidea - Used for High-Speeed OTG on Qualcomm SoCs
  • ST/Ericsson
  • Mentor Graphics - Inventra IP
    • used by TI DaVinci (35xx, 644x ...), OMAP 243x, OMAP 3 TSUB 6010
    • used by Analog Devices parts and Allwinners SoCs

Acronyms

ACA
Accessory Charger Adapter
ACM
Abstract Control Model
CDC
Communications Device Class - class of peripheral devices for communicating data between host and device
CI
Chipidea
DRD
Dual-Role Device
DWC3
Synopsys DesignWare C3 IP block (used by a lot of chip)
EHCI
Enhanced host controller interface (for High Speed)
EP
Endpoint
FS
Full-Speed (USB 1.0)
FSM
Finite State Machine - a set of states and state transitions for different modes of operation for the USB controller and PHY. States include things like B_IDLE, B_SRP_INIT, B_PERIPHERAL, B_WAIT_ACON, B_HOST, A_IDLE, A_WAIT_VRISE, A_WAIT_BCON, A_HOST, A_SUSPEND, A_PERIPHERAL, A_WAIT_VFALL, A_VBUS_ERR;OTG: On-the-go - a port that can switch between device (gadget) and host mode
HCD
host controller driver
HDRC
High-Speed Dual-Role Controller (for OTG)
HS
High-Speed (USB 2.0)
HSIC
High-Speed Inter-Chip - USB bus designed for on-board communications (not external to device)

HSIC (High-Speed Inter-Chip) is an industry standard for USB chip-to-chip interconnect with a 2-signal (strobe, data) source synchronous serial interface using 240 MHz DDR signaling to provide only high-speed (480 Mbps data rate). Low power can be achieved by using it with 1.2 V LVCMOS signaling levels instead of the 3.3 V signaling requirement. Both data and strobe are bi-directional utilizing NRZI encoding. In addition, HSIC interface is always operated at high speed, 480 Mbps. Hence, no high-speed chirp protocol is needed during enumeration. HSIC USB is fully compatible with existing USB software stacks and provides all data transfer needs through a single unified USB software stack.[1]

ID
ID pin on an OTG cable or port
LS
Low-Speed (USB 1.0)
MUSB
Mentor USB (/Multipoint USB?) - Inventra
OHCI
Open host controller interface (for Full-speed and Low-speed)
PHY
Physical layer interface (transceiver) - the hardware (or interface to it) that arranges bits for communication on the USB bus
SS
Super-Speed (USB 3.0)
UDC
USB device controller
ULPI
UTMI Low-Pin Interface - A specification for UTMI that uses less pins
URB
USB Request Block
UTMI
USB 2.0 Transceiver Macrocell Interface - a standard for registers for talking to a USB 2.0 Transceiver (phy)
VBUS
Voltage Bus (one of the lines on USB cable or port)
XHCI
eXtensible Host Controller Interface (for Super Speed)

device = peripheral = gadget host is usually the side that provides