BeagleBoard/GSoC/BeagleWire software support

About me
First name: Patryk Surname: Mężydło E-Mail: mezydlo.p@gmail.com IRC nickname: pmezydlo Programming Languages: C, C++, Python, Verilog, Assembler Interests and hobbies: Electronic, Embedded systems, FPGA, Judo, Walking Native language: Polish Other languages: English Timezone: CET ''GitHub: My Github profile Linkedin: My LinkedIn profile Work hours: 10:00-22:00 (CET) Previous GSoC participation: SPI slave driver implementation Currently I am in my third year of engineering studies at Gdańsk University of Technology in Poland. This is the second edition of GSoC in which I am participating. The first edition gave me the opportunity to gain a lot of valuable experience. I would like to continue my cooperation with BeagleBoard.org community. During the first edition I have been developing SPI_slave_driver_implementation project, which gave me a lot experience in the subject of linux drivers. I hope that this knowledge will prove to be helpful this year.

BeagleWire (FPGA cape)
The BeagleWire is an FPGA development platform that has been designed for use with BeagleBone boards. BeagleWire is a cape on which there is FPGA device - Lattice iCE40HX. The Lattice iCE40 is a family of FPGAs with a minimalistic architecture and very regular structure, designed for low-cost, high-volume consumer and system applications. The significance of FPGAs is continuously increasing, as they are more and more often used for supporting work of ARM processors. BeagleWire does not require external tools (JTAG) and the whole software is Open Source. iCE40 is an energy saving device, allowing to work with small batteries. FPGA cape allows easy and low cost start for beginners who would like to take their first steps in working with FPGAs. The developed software will be an easy and, at the same time, efficient tool for communication with FPGA. At this point FPGA will be able to meet the requirements of even more advanced applications. The BeagleWire creates a powerful and versatile digital cape for users to create their imaginative digital designs. BeagleWire features:
 * FPGA: Lattice iCE40HX4K - TQFP 144 Package,
 * 32 MB SDRAM,
 * BeagleBoard optimized,
 * GPIO,
 * 8x Leds,
 * 50Mhz external clock,
 * 4 layer PCB optimized design to support maximum performance for high bandwidth applications,
 * compatible with BeagleBone Black, BeagleBone Black Wireless, SeeedStudio BeagleBone Green, SeeedStudio BeagleBone Green Wireless, SanCloud BeagleBone Enhanced, element14 BeagleBone Black Industrial,
 * does not require external tools (JTAG),
 * minimalistic architecture and very regular structure,
 * energy saving device allows to work with small batteries,
 * lower application costs,
 * fully open-source toolchain,
 * SPI and GPMC port access from the Beaglebone,

BeagleWire software support
The task is to create software support for FPGA cape (based on iCE40 device). The completed project will provide the BeagleBoard.org community with easy to implement and powerful tools for realization of projects based on Programmable Logic Device(FPGA), which will surely increase the number of applications based on it. Although there already is a cape for BeagleBone involving FPGA device(LOGIBONE), LOGIBONE has several weaknesses which are not the case in FPGA cape based on iCE40 device.



BeagleWire software support project advantages:
 * fully open source software(synthesis HDL language),
 * easy to implement software,
 * many simple and more advanced examples,
 * extensive and comprehensive documentation on how to create application,
 * support for Python scripts (Python extension),
 * support for C application (C library),

Project implementation
Main Goals: Detailed description of each goal: 1. Create the lowest layer of bridge driver For communication between FPGA and ARM, I plan to use the GPMC. GPMC controller is configured from the DTS file. This is an easy and efficient solution. Gpmc pins are brought out to BeagleBone P8/P9 headers. AM335x datasheets: The general-purpose memory controller (GPMC)[1] is a unified memory controller dedicated to interfacing external memory devices: SRAM-like memories and application-specific integrated circuit (ASIC) devices, asynchronous, synchronous, and page mode (only available in non-multiplexed mode) burst NOR flash devices, NAND Flash, Pseudo-SRAM devices.
 * 1) Create the lowest layer of bridge driver
 * 2) Create Verilog bridge module allowing to connect user's Verilog module with ARM processor.
 * 3) Support for IRQ signals in both directions (from and to FPGA),
 * 4) Integration open source programming tools (iCE40 programming driver) with BeagleBone linux images (BeagleBone automatically loaded required DTS, EEPROM Cape, porting the icestorm toolchain to the BeagleBone Black),
 * 5) Python Extension and C Library which allows easy to develop application using the FPGA (copying memory blocks, capture interrupts, etc),
 * 6) Verilog examples,
 * 7) Extensive documentation,

Connecting BeagleWire with BeagleBone:



Communication is going to be mapped in processor’s memory, thus allowing an easy access using simple read and write operations. Bridge device will be described in DTS file. The next task is to write kernel driver which will be connected to FPGA kernel subsystem(FPGA subsystem). After compiling an image with added modules (config file) and loading DTS, communication with FPGA is like a typical operation on a file (/dev/FPGA).

2.Create Verilog bridge module allowing to connect user's Verilog module with ARM processor The task is to create a module which is able to read GPMC interface signals, providing an easy way to the exchange of data with user's logic. I intended to create two different solutions. Unfortunately, the amount of logic in iCE40 is not too big, as in the largest version it is only 8000 LUTs. Solutions should be as optimal as possible, because I would not like to create a bridge module that would take up more than 10% of the FPGA logic.

First solution:

Second solution: The second solution uses much less logic than the previous solution. It consists of exchanging data directly from the GPMC bus. In this solution, we bypass the address. Coupled with the interrupt, this solution can work efficiently.