Flameman/spartan3-3s500e

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= spartan3s500e =


 * device: xc3s500e-4fg320
 * package: 4fg320

overview

 * a pretty intro video from youtube

power

 * voltage: +5V
 * current: 1..2A
 * polarity: (+)

pin out, constraints
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ; NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ; NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ; NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ; NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ; NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%; NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ; NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ; NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ; NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ; NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ; NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ; NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ; NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ; NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ; NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ; NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ; NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "LED<0>" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<1>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ; NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ; NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ; NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ; NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ; NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ; NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ; NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ; NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ; NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ; NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ; NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ; NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ; NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ; NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ; NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ; NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ; NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ; NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ; NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ; NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ; NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ; NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ; NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ; NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ; NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ; NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ; NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ; NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ; NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ; NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ; NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ; NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ; NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ; CONFIG PROHIBIT = D2; CONFIG PROHIBIT = G4; CONFIG PROHIBIT = J6; CONFIG PROHIBIT = L5; CONFIG PROHIBIT = R4; NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ; NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ; NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ; NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ; NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ; NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ; NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ; NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 * 1) SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
 * 2) ==== Analog-to-Digital Converter (ADC) ====
 * 3) some connections shared with SPI Flash, DAC, ADC, and AMP
 * 1) ==== Analog-to-Digital Converter (ADC) ====
 * 2) some connections shared with SPI Flash, DAC, ADC, and AMP
 * 1) ==== Programmable Gain Amplifier (AMP) ====
 * 2) some connections shared with SPI Flash, DAC, ADC, and AMP
 * 1) ==== Pushbuttons (BTN) ====
 * 1) ==== Clock inputs (CLK) ====
 * 1) Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
 * 1) ==== Digital-to-Analog Converter (DAC) ====
 * 2) some connections shared with SPI Flash, DAC, ADC, and AMP
 * 1) ==== 1-Wire Secure EEPROM (DS)
 * 1) ==== Ethernet PHY (E) ====
 * 1) ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
 * 1) ==== FX2 Connector (FX2) ====
 * 1) These four connections are shared with the J1 6-pin accessory header
 * 1) These four connections are shared with the J2 6-pin accessory header
 * 1) These four connections are shared with the J4 6-pin accessory header
 * 1) The discrete LEDs are shared with the following 8 FX2 connections
 * 2) NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 3) NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 4) NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 5) NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 6) NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 7) NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 8) NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 9) NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
 * 1) ==== 6-pin header J1 ====
 * 2) These are shared connections with the FX2 connector
 * 3) NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 4) NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 5) NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 6) NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 7) ==== 6-pin header J2 ====
 * 8) These are shared connections with the FX2 connector
 * 9) NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 10) NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 11) NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 12) NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 13) ==== 6-pin header J4 ====
 * 14) These are shared connections with the FX2 connector
 * 15) NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 16) NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 17) NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 18) NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
 * 19) ==== Character LCD (LCD) ====
 * 1) LCD data connections are shared with StrataFlash connections SF_D<11:8>
 * 2) NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 * 3) NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 * 4) NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 * 5) NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
 * 6) ==== Discrete LEDs (LED) ====
 * 7) These are shared connections with the FX2 connector
 * 1) ==== PS/2 Mouse/Keyboard Port (PS2) ====
 * 1) ==== Rotary Pushbutton Switch (ROT) ====
 * 1) ==== RS-232 Serial Ports (RS232) ====
 * 1) ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
 * 1) Path to allow connection to top DCM connection
 * 1) Prohibit VREF pins
 * 1) ==== Intel StrataFlash Parallel NOR Flash (SF) ====
 * 1) ==== STMicro SPI serial Flash (SPI) ====
 * 2) some connections shared with SPI Flash, DAC, ADC, and AMP
 * 1) ==== Slide Switches (SW) ====
 * 1) ==== VGA Port (VGA) ====
 * 1) ==== Xilinx CPLD (XC) ====

useful links

 * youtube

Xilinx ISE inside VirtualBOX
Xilinx does not support Mac OS X and the USB platform cable did not seem to work inside the Windows and Linux virtual machines. The problem is that the USB cable changes its identity, its PRODUCT ID, from 0x000f to 0x0008 after its firmware has been loaded, causing the connection to the virtual machine to drop. The solution is to put in two capture filters, one with each ID.

cray1

 * Verilog implementation of the classic Cray-1

If you don't have a Spartan 3E you can check this project out

rekonstrukt, Maisforth Forth System09 6809

 * Forth CPU
 * Z80 system on chip, good to play pacman

Spartan-3E FPGA Starter Kit Board Design Examples

 * Kit Board Design Examples

ZPU was ported to this board, ZPUino should be follow

 * ZPU-s3e-200