Flameman/routerboard-rb532

= RouterBoard-rb532-Flameman =

Note
i'm developing for this board, the wiki page will be improved soon

feel free to contact me (see the contact below)

Introduction
The Target-goal of this page is
 * install gentoo-mipsel into microdrive
 * make the board able to boot from it
 * describe how to build a jtag cable (to debug and recover from "Brickage")
 * describe something useful with you can do with the board
 * describe other Operating Systems avalaible for the board

logical steps about installing gentoo
 * add the JTAG connector at J10 (you could skip it, it is suggested)
 * build the JTAG cable (you could skip it, it is suggested))
 * study the bootloader
 * make partitions on the microdrive
 * populate them
 * set the bootloader environment to boot from the microdrive

People you could contact if you need help

 * flameman, i'm currently use this board for a project, email
 * msn daredevil-coder@hotmail.it
 * email flamemaniii@gmail.com
 * irc.nick flameman (channel #edev, #gentoo-ppc)
 * you ... if you want ;-)

About the board
rb532 is a shortened name for the routerboard

you could get your board from http://routerboard.com/rb500.html

see the nearest reseller of the area where you live mind a brand new boards costs 140Euro + shipping and VAT cheaper way requires (fortune and) ebay searched for

Overview
The board consists of:


 * CPU IDT MIPS 79RC32434, a solid & smart implementation of the mipsel little endian MIPS 32 4Kcore CPU architecture, running at 400mhz (adjustable from 200 to 400MHz; 400MHz default and recommended)
 * RAM soldered 64MB DDR onboard memory chip
 * LAN On-chip 3 ethernet: One IDT Korina 10/100 Mbit/s Fast Ethernet port supporting Auto-MDI/X, Two VIA VT6105 10/100 Mbit/s Fast Ethernet ports supporting Auto-MDI/X.
 * UART One DB9 RS232C asynchronous serial port, speeds up to 230k, tested up to 115200bps
 * miniPCI Two MiniPCI Type IIIA/IIIB slots
 * CF support for IBM/Hitachi Microdrive (/dev/cfa)
 * ROM 1Mbit NAND flash where it is stored the bootloader
 * POWER IEEE802.3af Power over Ethernet: 12V or 48V DC, Power jack/header 6..22V or 25..56V DC jumper selectable. PoE does not support power over datalines
 * '''System PCB 14.0 cm x 14.0 cm
 * RTC the real time clock chip is missing
 * LED Power, 2 LED pairs for MiniPCI slots, 1 user LED
 * Watchdog IDT internal SoC hardware watchdog timer

NOTE: from the base configuration of 3 Ethernet ports and 2 MiniPCI slots (for wireless cards) it can be extended by using daughterboards for four more MiniPCI slots, or even up to a total of 15 interfaces (9 Ethernet ports and 6 MiniPCI slots). A wide range of accepted input power means that you can connect to almost any direct current power source you already have on site. It also can be powered through an Ethernet port using Power-over-Ethernet technology (802.3af) or passive non-standard PoE.

NOTE2: there is a daughterboard for the RB532. It is called RouterBOARD 564, and It attaches to the RB532 by means of special daughterboard connector and adds four more MiniPCI slots and six ethernet ports. You can not use more than two AR5414 chipset (e.g. R52) cards in RB/564. If you want to use three or four miniPCI cards in RB/564, you should use other chipset based ones for those extra slots, like CM9. For example, two R52 + two CM9 is OK, four CM9 is also OK, but not three or four R52.

Memory Locations
memory map of the board will be added as soon as possible

Open questions -- 1) how/where is ram mapped ?

2) how/where is microdrive mapped ?

3) how/where is pci mapped ?

3) what is the bootstrap addr of the flash ?

...

Problems
...

Images of the board


also see a detailed imate @ www routerboard.com/img/rb500_l.jpg

download
kernel 2.6.22 full tested and working [[Media:kernel-gentoo-rb532.gz|kernel-gentoo-rb532.gz]] (suggested for production)

interesting diff
diff -urN a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c --- a/arch/mips/rb532/devices.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/rb532/devices.c	2008-11-15 17:43:28.000000000 +0100 @@ -34,21 +34,11 @@ - -#define ETH0_DMA_RX_IRQ  	(GROUP1_IRQ_BASE + 0) -#define ETH0_DMA_TX_IRQ  	(GROUP1_IRQ_BASE + 1) -#define ETH0_RX_OVR_IRQ  	(GROUP3_IRQ_BASE + 9) -#define ETH0_TX_UND_IRQ  	(GROUP3_IRQ_BASE + 10) +#include  -/* NAND definitions */ -#define GPIO_RDY (1 << 0x08) -#define GPIO_WPX (1 << 0x09) -#define GPIO_ALE (1 << 0x0a) -#define GPIO_CLE (1 << 0x0b) - static struct resource korina_dev0_res[] = { { 		.name = "korina_regs", @@ -94,15 +84,13 @@ }; static struct platform_device korina_dev0 = { -	.id = 0, +	.id = -1, .name = "korina", .dev.platform_data = &korina_dev0_data, .resource = korina_dev0_res, .num_resources = ARRAY_SIZE(korina_dev0_res), }; -#define CF_GPIO_NUM 13 - static struct resource cf_slot0_res[] = { { 		.name = "cf_membase", @@ -116,11 +104,11 @@ }; static struct cf_device cf_slot0_data = { -	.gpio_pin = 13 +	.gpio_pin = CF_GPIO_NUM }; static struct platform_device cf_slot0 = { -	.id = 0, +	.id = -1, .name = "pata-rb532-cf", .dev.platform_data = &cf_slot0_data, .resource = cf_slot0_res, @@ -130,7 +118,7 @@ /* Resources and device for NAND */ static int rb532_dev_ready(struct mtd_info *mtd) { -	return readl(IDT434_REG_BASE + GPIOD) & GPIO_RDY; +	return gpio_get_value(GPIO_RDY); } static void rb532_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) @@ -185,7 +173,7 @@ static struct platform_device rb532_led = { .name = "rb532-led", -	.id = 0, +	.id = -1, }; static struct gpio_keys_button rb532_gpio_btn[] = { @@ -292,7 +280,7 @@ { 	/* Look for the CF card reader */ if (!readl(IDT434_REG_BASE + DEV1MASK)) -		rb532_devs[1] = NULL; +		rb532_devs[2] = NULL;	/* disable cf_slot0 at index 2 */ else { cf_slot0_res[0].start = readl(IDT434_REG_BASE + DEV1BASE); diff -urN a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c --- a/arch/mips/rb532/gpio.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/rb532/gpio.c	2008-11-15 17:43:28.000000000 +0100 @@ -27,28 +27,27 @@ */ -#include  -#include  -#include  - -#include  +#include  +#include  -struct rb532_gpio_reg __iomem *rb532_gpio_reg0; -EXPORT_SYMBOL(rb532_gpio_reg0); +struct rb532_gpio_chip { +	struct gpio_chip chip; +	void __iomem	 *regbase; +}; struct mpmc_device dev3; static struct resource rb532_gpio_reg0_res[] = { { 		.name 	= "gpio_reg0", -		.start 	= (u32)(IDT434_REG_BASE + GPIOBASE), -		.end 	= (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)), +		.start 	= REGBASE + GPIOBASE, +		.end 	= REGBASE + GPIOBASE + sizeof(struct rb532_gpio_reg) - 1, .flags 	= IORESOURCE_MEM, } }; @@ -56,8 +55,8 @@ static struct resource rb532_dev3_ctl_res[] = { { 		.name	= "dev3_ctl", -		.start	= (u32)(IDT434_REG_BASE + DEV3BASE), -		.end	= (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)), +		.start	= REGBASE + DEV3BASE, +		.end	= REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1, .flags	= IORESOURCE_MEM, } }; @@ -70,7 +69,7 @@ 	spin_lock_irqsave(&dev3.lock, flags); -	data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs); +	data = readl(IDT434_REG_BASE + reg_offs); for (i = 0; i != len; ++i) { if (val & (1 << i)) data |= (1 << (i + bit)); @@ -108,114 +107,166 @@ } EXPORT_SYMBOL(get_latch_u5); -int rb532_gpio_get_value(unsigned gpio) +/* rb532_set_bit - sanely set a bit + * + * bitval: new value for the bit + * offset: bit index in the 4 byte address range + * ioaddr: 4 byte aligned address being altered + */ +static inline void rb532_set_bit(unsigned bitval, +		unsigned offset, void __iomem *ioaddr) { -	return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio); -} -EXPORT_SYMBOL(rb532_gpio_get_value); +	unsigned long flags; +	u32 val; -void rb532_gpio_set_value(unsigned gpio, int value) -{ -	unsigned tmp; +	bitval = !!bitval;             /* map parameter to {0,1} */ + +	local_irq_save(flags); -	tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio); -	if (value) -		tmp |= 1 << gpio; +	val = readl(ioaddr); +	val &= ~( ~bitval << offset );  /* unset bit if bitval == 0 */ +	val |= (  bitval << offset );   /* set bit if bitval == 1 */ +	writel(val, ioaddr); -	writel(tmp, (void *)&rb532_gpio_reg0->gpiod); +	local_irq_restore(flags); } -EXPORT_SYMBOL(rb532_gpio_set_value); -int rb532_gpio_direction_input(unsigned gpio) +/* rb532_get_bit - read a bit + * + * returns the boolean state of the bit, which may be > 1 + */ +static inline int rb532_get_bit(unsigned offset, void __iomem *ioaddr) { -	writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio), -	      (void *)&rb532_gpio_reg0->gpiocfg); - -	return 0; +	return (readl(ioaddr) & (1 << offset)); } -EXPORT_SYMBOL(rb532_gpio_direction_input); -int rb532_gpio_direction_output(unsigned gpio, int value) +/* + * Return GPIO level */ +static int rb532_gpio_get(struct gpio_chip *chip, unsigned offset) { -	gpio_set_value(gpio, value); -	writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio), -	      (void *)&rb532_gpio_reg0->gpiocfg); +	struct rb532_gpio_chip	*gpch; -	return 0; +	gpch = container_of(chip, struct rb532_gpio_chip, chip); +	return rb532_get_bit(offset, gpch->regbase + GPIOD); } -EXPORT_SYMBOL(rb532_gpio_direction_output); -void rb532_gpio_set_int_level(unsigned gpio, int value) +/* + * Set output GPIO level + */ +static void rb532_gpio_set(struct gpio_chip *chip, +				unsigned offset, int value) { -	unsigned tmp; +	struct rb532_gpio_chip	*gpch; -	tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio); -	if (value) -		tmp |= 1 << gpio; -	writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel); +	gpch = container_of(chip, struct rb532_gpio_chip, chip); +	rb532_set_bit(value, offset, gpch->regbase + GPIOD); } -EXPORT_SYMBOL(rb532_gpio_set_int_level); -int rb532_gpio_get_int_level(unsigned gpio) +/* + * Set GPIO direction to input + */ +static int rb532_gpio_direction_input(struct gpio_chip *chip, unsigned offset) { -	return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio); +	struct rb532_gpio_chip	*gpch; + +	gpch = container_of(chip, struct rb532_gpio_chip, chip); + +	if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) +		return 1;	/* alternate function, GPIOCFG is ignored */ + +	rb532_set_bit(0, offset, gpch->regbase + GPIOCFG); +	return 0; } -EXPORT_SYMBOL(rb532_gpio_get_int_level); -void rb532_gpio_set_int_status(unsigned gpio, int value) +/* + * Set GPIO direction to output + */ +static int rb532_gpio_direction_output(struct gpio_chip *chip, +					unsigned offset, int value) { -	unsigned tmp; +	struct rb532_gpio_chip	*gpch; + +	gpch = container_of(chip, struct rb532_gpio_chip, chip); -	tmp = readl(&rb532_gpio_reg0->gpioistat); -	if (value) -		tmp |= 1 << gpio; -	writel(tmp, (void *)&rb532_gpio_reg0->gpioistat); +	if (rb532_get_bit(offset, gpch->regbase + GPIOFUNC)) +		return 1;	/* alternate function, GPIOCFG is ignored */ + +	/* set the initial output value */ +	rb532_set_bit(value, offset, gpch->regbase + GPIOD); + +	rb532_set_bit(1, offset, gpch->regbase + GPIOCFG); +	return 0; } -EXPORT_SYMBOL(rb532_gpio_set_int_status); -int rb532_gpio_get_int_status(unsigned gpio) +static struct rb532_gpio_chip rb532_gpio_chip[] = { +	[0] = { +		.chip = { +			.label			= "gpio0", +			.direction_input	= rb532_gpio_direction_input, +			.direction_output	= rb532_gpio_direction_output, +			.get			= rb532_gpio_get, +			.set			= rb532_gpio_set, +			.base			= 0, +			.ngpio			= 32, +		}, +	}, +}; + +/* + * Set GPIO interrupt level + */ +void rb532_gpio_set_ilevel(int bit, unsigned gpio) { -	return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio); +	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOILEVEL); } -EXPORT_SYMBOL(rb532_gpio_get_int_status); +EXPORT_SYMBOL(rb532_gpio_set_ilevel); -void rb532_gpio_set_func(unsigned gpio, int value) +/* + * Set GPIO interrupt status + */ +void rb532_gpio_set_istat(int bit, unsigned gpio) { -	unsigned tmp; - -	tmp = readl(&rb532_gpio_reg0->gpiofunc); -	if (value) -		tmp |= 1 << gpio; -	writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc); +	rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOISTAT); } -EXPORT_SYMBOL(rb532_gpio_set_func); +EXPORT_SYMBOL(rb532_gpio_set_istat); -int rb532_gpio_get_func(unsigned gpio) +/* + * Configure GPIO alternate function + */ +static void rb532_gpio_set_func(int bit, unsigned gpio) { -	return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio); +      rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); } -EXPORT_SYMBOL(rb532_gpio_get_func); int __init rb532_gpio_init(void) { -	rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start, -				rb532_gpio_reg0_res[0].end - -				rb532_gpio_reg0_res[0].start); +	struct resource *r; + +	r = rb532_gpio_reg0_res; +	rb532_gpio_chip->regbase = ioremap_nocache(r->start, r->end - r->start); -	if (!rb532_gpio_reg0) { +	if (!rb532_gpio_chip->regbase) { printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); return -ENXIO; } -	dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, -				rb532_dev3_ctl_res[0].end - -				rb532_dev3_ctl_res[0].start); +	/* Register our GPIO chip */ +	gpiochip_add(&rb532_gpio_chip->chip); + +	r = rb532_dev3_ctl_res; +	dev3.base = ioremap_nocache(r->start, r->end - r->start); if (!dev3.base) { printk(KERN_ERR "rb532: cannot remap device controller 3\n"); return -ENXIO; } +	/* configure CF_GPIO_NUM as CFRDY IRQ source */ +	rb532_gpio_set_func(0, CF_GPIO_NUM); +	rb532_gpio_direction_input(&rb532_gpio_chip->chip, CF_GPIO_NUM); +	rb532_gpio_set_ilevel(1, CF_GPIO_NUM); +	rb532_gpio_set_istat(0, CF_GPIO_NUM); + 	return 0; } arch_initcall(rb532_gpio_init); diff -urN a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c --- a/arch/mips/rb532/irq.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/rb532/irq.c	2008-11-15 17:43:28.000000000 +0100 @@ -45,7 +45,7 @@ -#include  +#include  struct intr_group { u32 mask;	/* mask of valid bits in pending/mask registers */ diff -urN a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c --- a/arch/mips/rb532/prom.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/rb532/prom.c	2008-11-15 17:43:28.000000000 +0100 @@ -37,12 +37,8 @@ -extern void __init setup_serial_port(void); - unsigned int idt_cpu_freq = 132000000; EXPORT_SYMBOL(idt_cpu_freq); -unsigned int gpio_bootup_state; -EXPORT_SYMBOL(gpio_bootup_state); static struct resource ddr_reg[] = { { @@ -108,9 +104,6 @@ 				mips_machtype = MACH_MIKROTIK_RB532; } -		if (match_tag(prom_argv[i], GPIO_TAG)) -			gpio_bootup_state = tag2ul(prom_argv[i], GPIO_TAG); - 		strcpy(cp, prom_argv[i]); cp += strlen(prom_argv[i]); } @@ -122,11 +115,6 @@ 		strcpy(cp, arcs_cmdline); cp += strlen(arcs_cmdline); } -	if (gpio_bootup_state & 0x02) -		strcpy(cp, GPIO_INIT_NOBUTTON); -	else -		strcpy(cp, GPIO_INIT_BUTTON); - 	cmd_line[CL_SIZE-1] = '\0'; strcpy(arcs_cmdline, cmd_line); diff -urN a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c --- a/arch/mips/rb532/serial.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/rb532/serial.c	2008-11-15 17:43:28.000000000 +0100 @@ -31,16 +31,16 @@ -#include  +#include  extern unsigned int idt_cpu_freq; static struct uart_port rb532_uart = { .type = PORT_16550A, .line = 0, -	.irq = RC32434_UART0_IRQ, +	.irq = UART0_IRQ, .iotype = UPIO_MEM, -	.membase = (char *)KSEG1ADDR(RC32434_UART0_BASE), +	.membase = (char *)KSEG1ADDR(REGBASE + UART0BASE), .regshift = 2 }; diff -urN a/arch/mips/rb532/setup.c b/arch/mips/rb532/setup.c --- a/arch/mips/rb532/setup.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/rb532/setup.c	2008-11-15 17:43:28.000000000 +0100 @@ -9,7 +9,7 @@ -#include  +#include  struct pci_reg __iomem *pci_reg; @@ -27,7 +27,7 @@ static void rb_machine_restart(char *command) { 	/* just jump to the reset vector */ -	writel(0x80000001, (void *)KSEG1ADDR(RC32434_REG_BASE + RC32434_RST)); +	writel(0x80000001, IDT434_REG_BASE + RST); ((void (*)(void)) KSEG1ADDR(0x1FC00000u)); } diff -urN a/arch/mips/rb532/time.c b/arch/mips/rb532/time.c --- a/arch/mips/rb532/time.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/rb532/time.c	2008-11-15 17:43:28.000000000 +0100 @@ -28,7 +28,6 @@ -#include  diff -urN linux-2.6.27.5/arch/mips/Kconfig linux-2.6.27.5.new/arch/mips/Kconfig --- linux-2.6.27.5/arch/mips/Kconfig	2008-11-07 18:55:34.000000000 +0100 +++ linux-2.6.27.5.new/arch/mips/Kconfig	2008-11-15 17:50:42.000000000 +0100 @@ -568,7 +568,7 @@ 	select SYS_SUPPORTS_LITTLE_ENDIAN select SWAP_IO_SPACE select BOOT_RAW -	select GENERIC_GPIO +	select ARCH_REQUIRE_GPIOLIB help Support the Mikrotik(tm) RouterBoard 532 series, based on the IDT RC32434 SoC. diff -urN a/include/asm-mips/mach-rc32434/gpio.h b/include-mips/asm/mach-rc32434/gpio.h --- a/include/asm-mips/mach-rc32434/gpio.h	2008-11-07 18:55:34.000000000 +0100 +++ b/include/asm-mips/mach-rc32434/gpio.h	2008-11-15 17:43:28.000000000 +0100 @@ -14,6 +14,16 @@ +#include  + +#define NR_BUILTIN_GPIO		32 + +#define gpio_get_value	__gpio_get_value +#define gpio_set_value	__gpio_set_value +#define gpio_cansleep	__gpio_cansleep + +#define gpio_to_irq(gpio)	(8 + 4 * 32 + gpio) +#define irq_to_gpio(irq)	(irq - (8 + 4 * 32)) struct rb532_gpio_reg { u32  gpiofunc;   /* GPIO Function Register @@ -61,66 +71,20 @@ /* PCI messaging unit */ +/* NAND GPIO signals */ +#define GPIO_RDY		8 +#define GPIO_WPX	9 +#define GPIO_ALE		10 +#define GPIO_CLE		11 + +/* Compact Flash GPIO pin */ +#define CF_GPIO_NUM		13 extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val); extern unsigned get_434_reg(unsigned reg_offs); extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); extern unsigned char get_latch_u5(void); - -extern int rb532_gpio_get_value(unsigned gpio); -extern void rb532_gpio_set_value(unsigned gpio, int value); -extern int rb532_gpio_direction_input(unsigned gpio); -extern int rb532_gpio_direction_output(unsigned gpio, int value); -extern void rb532_gpio_set_int_level(unsigned gpio, int value); -extern int rb532_gpio_get_int_level(unsigned gpio); -extern void rb532_gpio_set_int_status(unsigned gpio, int value); -extern int rb532_gpio_get_int_status(unsigned gpio); - - -/* Wrappers for the arch-neutral GPIO API */ - -static inline int gpio_request(unsigned gpio, const char *label) -{ -	/* Not yet implemented */ -	return 0; -} - -static inline void gpio_free(unsigned gpio) -{ -	/* Not yet implemented */ -} - -static inline int gpio_direction_input(unsigned gpio) -{ -	return rb532_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ -	return rb532_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ -	return rb532_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ -	rb532_gpio_set_value(gpio, value); -} - -static inline int gpio_to_irq(unsigned gpio) -{ -	return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ -	return irq; -} - -/* For cansleep */ -#include  +extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); +extern void rb532_gpio_set_istat(int bit, unsigned gpio); diff -urN a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h --- a/include/asm-mips/mach-rc32434/irq.h	2008-11-07 18:55:34.000000000 +0100 +++ b/include/asm-mips/mach-rc32434/irq.h	2008-11-15 17:43:28.000000000 +0100 @@ -4,5 +4,30 @@ +#include <asm/mach-rc32434/rb.h> + +/* Interrupt Controller */ +#define IC_GROUP0_PEND		(REGBASE + 0x38000) +#define IC_GROUP0_MASK		(REGBASE + 0x38008) +#define IC_GROUP_OFFSET		0x0C + +#define NUM_INTR_GROUPS		5 + +/* 16550 UARTs */ +#define GROUP0_IRQ_BASE		8	/* GRP2 IRQ numbers start here */ +					/* GRP3 IRQ numbers start here */ +#define GROUP1_IRQ_BASE		(GROUP0_IRQ_BASE + 32) +					/* GRP4 IRQ numbers start here */ +#define GROUP2_IRQ_BASE		(GROUP1_IRQ_BASE + 32) +					/* GRP5 IRQ numbers start here */ +#define GROUP3_IRQ_BASE		(GROUP2_IRQ_BASE + 32) +#define GROUP4_IRQ_BASE		(GROUP3_IRQ_BASE + 32) + +#define UART0_IRQ		(GROUP3_IRQ_BASE + 0) + +#define ETH0_DMA_RX_IRQ  	(GROUP1_IRQ_BASE + 0) +#define ETH0_DMA_TX_IRQ  	(GROUP1_IRQ_BASE + 1) +#define ETH0_RX_OVR_IRQ  	(GROUP3_IRQ_BASE + 9) +#define ETH0_TX_UND_IRQ  	(GROUP3_IRQ_BASE + 10) diff -urN a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h --- a/include/asm-mips/mach-rc32434/prom.h	2008-11-07 18:55:34.000000000 +0100 +++ b/include/asm-mips/mach-rc32434/prom.h	2008-11-15 17:43:28.000000000 +0100 @@ -28,14 +28,10 @@ -#define GPIO_INIT_NOBUTTON	"" -#define GPIO_INIT_BUTTON	" 2" - -#define GPIO_TAG		"gpio=" diff -urN a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h --- a/include/asm-mips/mach-rc32434/rb.h	2008-11-07 18:55:34.000000000 +0100 +++ b/include/asm-mips/mach-rc32434/rb.h	2008-11-15 17:43:28.000000000 +0100 @@ -17,7 +17,10 @@ -#define IDT434_REG_BASE	((volatile void *) KSEG1ADDR(0x18000000)) +#define REGBASE		0x18000000 +#define IDT434_REG_BASE	((volatile void *) KSEG1ADDR(REGBASE)) +#define UART0BASE	0x58000 +#define RST		(1 << 15) @@ -37,12 +40,14 @@ -#define GPIOCFG		0x050004 -#define GPIOD		0x050008 -#define GPIOILEVEL	0x05000C -#define GPIOISTAT	0x050010 -#define GPIONMIEN	0x050014 -#define IMASK6		0x038038 +/* Offsets relative to GPIOBASE */ +#define GPIOFUNC	0x00 +#define GPIOCFG		0x04 +#define GPIOD		0x08 +#define GPIOILEVEL	0x0C +#define GPIOISTAT	0x10 +#define GPIONMIEN	0x14 +#define IMASK6		0x38 diff -urN a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h --- a/include/asm-mips/mach-rc32434/rc32434.h	2008-11-07 18:55:34.000000000 +0100 +++ b/include/asm-mips/mach-rc32434/rc32434.h	2008-11-15 17:43:28.000000000 +0100 @@ -8,37 +8,7 @@ -#define RC32434_REG_BASE	0x18000000 -#define RC32434_RST		(1 << 15) - -#define MIPS_CPU_TIMER_IRQ	7 - -/* Interrupt Controller */ -#define IC_GROUP0_PEND		(RC32434_REG_BASE + 0x38000) -#define IC_GROUP0_MASK		(RC32434_REG_BASE + 0x38008) -#define IC_GROUP_OFFSET		0x0C - -#define NUM_INTR_GROUPS		5 - -/* 16550 UARTs */ -#define GROUP0_IRQ_BASE		8	/* GRP2 IRQ numbers start here */ -					/* GRP3 IRQ numbers start here */ -#define GROUP1_IRQ_BASE		(GROUP0_IRQ_BASE + 32) -					/* GRP4 IRQ numbers start here */ -#define GROUP2_IRQ_BASE		(GROUP1_IRQ_BASE + 32) -					/* GRP5 IRQ numbers start here */ -#define GROUP3_IRQ_BASE		(GROUP2_IRQ_BASE + 32) -#define GROUP4_IRQ_BASE		(GROUP3_IRQ_BASE + 32) - - -#ifdef __MIPSEB__ -#define RC32434_UART0_BASE	(RC32434_REG_BASE + 0x58003) -#else -#define RC32434_UART0_BASE	(RC32434_REG_BASE + 0x58000) -#endif - -#define RC32434_UART0_IRQ	(GROUP3_IRQ_BASE + 0) /* cpu pipeline flush */ static inline void rc32434_sync(void) @@ -46,16 +16,4 @@ 	__asm__ volatile ("sync"); } -static inline void rc32434_sync_udelay(int us) -{ -	__asm__ volatile ("sync"); -	udelay(us); -} - -static inline void rc32434_sync_delay(int ms) -{ -	__asm__ volatile ("sync"); -	mdelay(ms); -} - --- a/arch/mips/pci/fixup-rc32434.c	2008-11-07 18:55:34.000000000 +0100 +++ b/arch/mips/pci/fixup-rc32434.c	2008-11-15 17:43:28.000000000 +0100 @@ -30,6 +30,7 @@ +#include <asm/mach-rc32434/irq.h> static int __devinitdata irq_map[2][12] = { {0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1},
 * 1) include <asm/mach-rc32434/rb.h>
 * 2) include <asm/mach-rc32434/integ.h>
 * 3) include <asm/mach-rc32434/gpio.h>
 * 1) define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET)
 * 2) define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET)
 * 1) include <linux/kernel.h>
 * 1) include <linux/init.h>
 * 2) include <linux/types.h>
 * 1) include <linux/spinlock.h>
 * 1) include <linux/platform_device.h>
 * 1) include <asm/mach-rc32434/rb.h>
 * 1) include <asm/mipsregs.h>
 * 2) include <asm/system.h>
 * 1) include <asm/mach-rc32434/ddr.h>
 * 2) include <asm/mach-rc32434/prom.h>
 * 1) include <linux/serial_8250.h>
 * 1) include <asm/serial.h>
 * 1) include <asm/time.h>
 * 2) include <linux/ioport.h>
 * 1) include <asm/mach-rc32434/pci.h>
 * 1) include <linux/timex.h>
 * 1) include <asm/mipsregs.h>
 * 1) include <asm/time.h>
 * 2) include <asm/mach-rc32434/rc32434.h>
 * 1) define _RC32434_GPIO_H_
 * 1) include <linux/types.h>
 * 1) define RC32434_PCI_MSU_GPIO	(1 << 13)
 * 1) endif /* _RC32434_GPIO_H_ */
 * 1) define NR_IRQS	256
 * 1) include <asm/mach-generic/irq.h>
 * 1) endif /* __ASM_RC32434_IRQ_H */
 * 1) define PROM_ENTRY(x)		(0xbfc00000 + ((x) * 8))
 * 1) define SR_NMI			0x00180000
 * 2) define SERIAL_SPEED_ENTRY	0x00000001
 * 1) define FREQ_TAG		"HZ="
 * 1) define KMAC_TAG		"kmac="
 * 2) define MEM_TAG			"mem="
 * 3) define BOARD_TAG		"board="
 * 1) include <linux/genhd.h>
 * 1) define DEV0BASE	0x010000
 * 2) define DEV0MASK	0x010004
 * 3) define DEV0C		0x010008
 * 1) define BTCS		0x010040
 * 2) define BTCOMPARE	0x010044
 * 3) define GPIOBASE	0x050000
 * 1) define LO_WPX		(1 << 0)
 * 2) define LO_ALE		(1 << 1)
 * 3) define LO_CLE		(1 << 2)
 * 1) include <linux/delay.h>
 * 2) include <linux/io.h>
 * 1) define IDT_CLOCK_MULT		2
 * 1) endif /* _ASM_RC32434_RC32434_H_ */
 * 1) include <linux/init.h>
 * 1) include <asm/mach-rc32434/rc32434.h>

gpio.c
arch.mips.rb532.gpio

001 /* 002 *  Miscellaneous functions for IDT EB434 board 003 * 004  *  2004 IDT Inc. (rischelp@idt.com) 005 *  2006 Phil Sutter <n0-1@freewrt.org> 006 *  2007 Florian Fainelli <florian@openwrt.org> 007 * 027  */ 028 029 #include <linux/kernel.h> 030 #include <linux/gpio.h> 031 #include <linux/init.h> 032 #include <linux/types.h> 033 #include <linux/pci.h> 034 #include <linux/spinlock.h> 035 #include <linux/io.h> 036 #include <linux/platform_device.h> 037 038 #include <asm/addrspace.h> 039 040 #include <asm/mach-rc32434/rb.h> 041 042 struct rb532_gpio_reg __iomem *rb532_gpio_reg0; 043 EXPORT_SYMBOL(rb532_gpio_reg0); 044 045 struct mpmc_device dev3; 046 047 static struct resource rb532_gpio_reg0_res[] = { 048        { 049                 .name   = "gpio_reg0", 050                .start  = (u32)(IDT434_REG_BASE + GPIOBASE), 051                .end    = (u32)(IDT434_REG_BASE + GPIOBASE + sizeof(struct rb532_gpio_reg)), 052                .flags  = IORESOURCE_MEM, 053        } 054 }; 055 056 static struct resource rb532_dev3_ctl_res[] = { 057        { 058                 .name   = "dev3_ctl", 059                .start  = (u32)(IDT434_REG_BASE + DEV3BASE), 060                .end    = (u32)(IDT434_REG_BASE + DEV3BASE + sizeof(struct dev_reg)), 061                .flags  = IORESOURCE_MEM, 062        } 063 }; 064 065 void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val) 066 { 067        unsigned long flags; 068        unsigned data; 069        unsigned i = 0; 070 071        spin_lock_irqsave(&dev3.lock, flags); 072 073        data = *(volatile unsigned *) (IDT434_REG_BASE + reg_offs); 074        for (i = 0; i != len; ++i) { 075                if (val & (1 << i)) 076                        data |= (1 << (i + bit)); 077                else 078                        data &= ~(1 << (i + bit)); 079        } 080         writel(data, (IDT434_REG_BASE + reg_offs)); 081 082        spin_unlock_irqrestore(&dev3.lock, flags); 083 } 084 EXPORT_SYMBOL(set_434_reg); 085 086 unsigned get_434_reg(unsigned reg_offs) 087 { 088        return readl(IDT434_REG_BASE + reg_offs); 089 } 090 EXPORT_SYMBOL(get_434_reg); 091 092 void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) 093 { 094        unsigned long flags; 095 096        spin_lock_irqsave(&dev3.lock, flags); 097 098        dev3.state = (dev3.state | or_mask) & ~nand_mask; 099        writel(dev3.state, &dev3.base); 100 101        spin_unlock_irqrestore(&dev3.lock, flags); 102 } 103 EXPORT_SYMBOL(set_latch_u5); 104 105 unsigned char get_latch_u5(void) 106 { 107        return dev3.state; 108 } 109 EXPORT_SYMBOL(get_latch_u5); 110 111 int rb532_gpio_get_value(unsigned gpio) 112 { 113        return readl(&rb532_gpio_reg0->gpiod) & (1 << gpio); 114 } 115 EXPORT_SYMBOL(rb532_gpio_get_value); 116 117 void rb532_gpio_set_value(unsigned gpio, int value) 118 { 119        unsigned tmp; 120 121        tmp = readl(&rb532_gpio_reg0->gpiod) & ~(1 << gpio); 122        if (value) 123                tmp |= 1 << gpio; 124 125        writel(tmp, (void *)&rb532_gpio_reg0->gpiod); 126 } 127 EXPORT_SYMBOL(rb532_gpio_set_value); 128 129 int rb532_gpio_direction_input(unsigned gpio) 130 { 131        writel(readl(&rb532_gpio_reg0->gpiocfg) & ~(1 << gpio), 132                (void *)&rb532_gpio_reg0->gpiocfg); 133 134        return 0; 135 } 136 EXPORT_SYMBOL(rb532_gpio_direction_input); 137 138 int rb532_gpio_direction_output(unsigned gpio, int value) 139 { 140        gpio_set_value(gpio, value); 141        writel(readl(&rb532_gpio_reg0->gpiocfg) | (1 << gpio), 142                (void *)&rb532_gpio_reg0->gpiocfg); 143 144        return 0; 145 } 146 EXPORT_SYMBOL(rb532_gpio_direction_output); 147 148 void rb532_gpio_set_int_level(unsigned gpio, int value) 149 { 150        unsigned tmp; 151 152        tmp = readl(&rb532_gpio_reg0->gpioilevel) & ~(1 << gpio); 153        if (value) 154                tmp |= 1 << gpio; 155        writel(tmp, (void *)&rb532_gpio_reg0->gpioilevel); 156 } 157 EXPORT_SYMBOL(rb532_gpio_set_int_level); 158 159 int rb532_gpio_get_int_level(unsigned gpio) 160 { 161        return readl(&rb532_gpio_reg0->gpioilevel) & (1 << gpio); 162 } 163 EXPORT_SYMBOL(rb532_gpio_get_int_level); 164 165 void rb532_gpio_set_int_status(unsigned gpio, int value) 166 { 167        unsigned tmp; 168 169        tmp = readl(&rb532_gpio_reg0->gpioistat); 170        if (value) 171                tmp |= 1 << gpio; 172        writel(tmp, (void *)&rb532_gpio_reg0->gpioistat); 173 } 174 EXPORT_SYMBOL(rb532_gpio_set_int_status); 175 176 int rb532_gpio_get_int_status(unsigned gpio) 177 { 178        return readl(&rb532_gpio_reg0->gpioistat) & (1 << gpio); 179 } 180 EXPORT_SYMBOL(rb532_gpio_get_int_status); 181 182 void rb532_gpio_set_func(unsigned gpio, int value) 183 { 184        unsigned tmp; 185 186        tmp = readl(&rb532_gpio_reg0->gpiofunc); 187        if (value) 188                tmp |= 1 << gpio; 189        writel(tmp, (void *)&rb532_gpio_reg0->gpiofunc); 190 } 191 EXPORT_SYMBOL(rb532_gpio_set_func); 192 193 int rb532_gpio_get_func(unsigned gpio) 194 { 195        return readl(&rb532_gpio_reg0->gpiofunc) & (1 << gpio); 196 } 197 EXPORT_SYMBOL(rb532_gpio_get_func); 198 199 int __init rb532_gpio_init(void) 200 { 201        rb532_gpio_reg0 = ioremap_nocache(rb532_gpio_reg0_res[0].start, 202                                 rb532_gpio_reg0_res[0].end - 203                                 rb532_gpio_reg0_res[0].start); 204 205        if (!rb532_gpio_reg0) { 206                printk(KERN_ERR "rb532: cannot remap GPIO register 0\n"); 207                return -ENXIO; 208        } 209 210         dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, 211                                 rb532_dev3_ctl_res[0].end - 212                                 rb532_dev3_ctl_res[0].start); 213 214        if (!dev3.base) { 215                printk(KERN_ERR "rb532: cannot remap device controller 3\n"); 216                return -ENXIO; 217        } 218 219         return 0; 220 } 221 arch_initcall(rb532_gpio_init);

About Gentoo
the kernel bootstrap from the micro drive



what/where

 * kernel 2.4.x there is a port of linux 2.4.30/31 that has been tested and it is perfectly working: see http://routerboard.com/files/linux-2.4.30-yaffs2.patch.gz, http://routerboard.com/files/linux-2.4.31.patch.gz
 * kernel 2.6.x
 * 2.6.22: in use on my board with success, and has it has been tested for a very long uptime it is known to be very robust (suggested for production)
 * 2.6.23: is under porting, see the git @ http://www.linux-mips.org/git?p=linux-routerboard.git;a=summary (actually i have an issue and it doesn't boot ... there is an issue with the firmware bootloader)
 * 2.6.24: no sup, repository romoved cause it still has the 2.6.23 issue
 * 2.6.26: interesting for the thickness feature, r3 is under development
 * 2.6.28: interesting for ext4, it's in my repository, r4 under development

dmesg
on 04-12-2007 i was able to compile a perfectly working kernel 2.6.22, here the dmesg

Version 2.6.22-manatnees-batman-mipsel-rb532 (root@queen-vittoria) (gcc version 4.1.2 (Gentoo 4.1.2 p1.0.2)) #6 Tue Dec 4 17:12:23 CET 2007 CPU revision is: 0001800a Determined physical RAM map: memory: 03fffa00 @ 00000400 (usable) Wasting 32 bytes for tracking 1 unused pages Initrd not found or empty - disabling initrd On node 0 totalpages: 16383 Normal zone: 127 pages used for memmap Normal zone: 0 pages reserved Normal zone: 16256 pages, LIFO batch:3 Built 1 zonelists. Total pages: 16256 Kernel command line: root=/dev/cfa3 console=ttyS0,9600 gpio=8191 kmac=00:0C:42:0E:8F:01 board=500r5 boot=1 korina mac = 00:0C:42:0E:8F:01 Primary instruction cache 8kB, physically tagged, 4-way, linesize 16 bytes. Primary data cache 8kB, 4-way, linesize 16 bytes. Synthesized TLB refill handler (20 instructions). Synthesized TLB load handler fastpath (32 instructions). Synthesized TLB store handler fastpath (32 instructions). Synthesized TLB modify handler fastpath (31 instructions). Initializing IRQ's: 168 out of 256 PID hash table entries: 256 (order: 8, 1024 bytes) calculating r4koff... 001e846c(1999980) CPU frequency 400.00 MHz Using 199.998 MHz high precision timer. Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 61120k/65528k available (2187k kernel code, 4348k reserved, 352k data, 120k init, 0k highmem) Calibrating delay loop... 398.95 BogoMIPS (lpj=1994752) Mount-cache hash table entries: 512 NET: Registered protocol family 16 PCI: Initializing PCI registering PCI controller with io_map_base unset NET: Registered protocol family 2 Time: MIPS clocksource has been installed. IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 2048 (order: 2, 16384 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes) TCP: Hash tables configured (established 2048 bind 2048) TCP reno registered Registering mini_fo version $Id$ JFFS2 version 2.2. (NAND) (SUMMARY) Â© 2001-2006 Red Hat, Inc. yaffs Dec  4 2007 17:07:52 Installing. io scheduler noop registered io scheduler deadline registered (default) Serial: 8250/16550 driver $Revision: 1.90 $ 2 ports, IRQ sharing disabled serial8250: ttyS0 at MMIO 0x0 (irq = 104) is a 16550A cf-mips module loaded cf-mips: resetting.. cf-mips: identify drive.. cf-mips: CF card detected, C/H/S=3968/16/63 sectors=3999744 (1953MB) cf-mips: detecting block size cf-mips: multiple sectors = 32 init done: cfa: cfa1 cfa2 cfa3 Using NAPI with weight 64 eth0: Rx IRQ 40, Tx IRQ 41, 00:0c:42:0e:8f:01 via-rhine.c:v1.10-LK1.4.3 2007-03-06 Written by Donald Becker PCI: Enabling device 0000:00:02.0 (0080 -> 0083) PCI: Setting latency timer of device 0000:00:02.0 to 64 io_map_base of root PCI bus 0000:00 unset. Trying to continue but you better fix this issue or report it to linux-mips@linux-mips.org or your vendor. eth1: VIA Rhine III at 0xb8800000, 00:0c:42:0e:8f:02, IRQ 142. eth1: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000. PCI: Enabling device 0000:00:03.0 (0080 -> 0083) PCI: Setting latency timer of device 0000:00:03.0 to 64 eth2: VIA Rhine III at 0xb8800100, 00:0c:42:0e:8f:03, IRQ 143. eth2: MII PHY found at address 1, status 0x7849 advertising 05e1 Link 0000. block2mtd: version $Revision: 1.30 $ NAND device: Manufacturer ID: 0xad, Chip ID: 0xf1 (Hynix NAND 128MiB 3,3V 8-bit) Scanning device for bad blocks Bad eraseblock 92 at 0x00b80000 Creating 2 MTD partitions on "NAND 128MiB 3,3V 8-bit": 0x00000000-0x00400000 : "Routerboard NAND boot" 0x00400000-0x08000000 : "rootfs" mtd: partition "rootfs" set to be root filesystem split_squasfs: no squashfs found in "NAND 128MiB 3,3V 8-bit" Registered led device: rb500led:amber nf_conntrack version 0.5.0 (511 buckets, 4088 max) ip_tables: (C) 2000-2006 Netfilter Core Team TCP vegas registered NET: Registered protocol family 1 NET: Registered protocol family 17 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> All bugs added by David S. Miller <davem@redhat.com> EXT3-fs: INFO: recovery required on readonly filesystem. EXT3-fs: write access will be enabled during recovery. kjournald starting. Commit interval 5 seconds EXT3-fs: recovery complete. EXT3-fs: mounted filesystem with ordered data mode. VFS: Mounted root (ext3 filesystem) readonly. Freeing unused kernel memory: 120k freed Algorithmics/MIPS FPU Emulator v1.5 EXT3 FS on cfa3, internal journal

@15-02-2009 i have to update the kernel to 2.6.26/2.6.28 (still under proof status in my repositories) and i am looking for {miniPCI-sATA, miniPCI-netwifi}

About devtools
@16-02-2009

you can ask me a working kernel tarball of the sources

actually development tools can be inspired

http://buildroot.uclibc.org/downloads/snapshots/

http://dev.gentoo.org/~vapier/CROSS-COMPILE-HOWTO

http://www.denx.de/cgi-bin/gitweb.cgi?p=linux-2.6-denx.git;a=blob;f=arch/mips/configs/rb532_defconfig;h=b2e1e0cb85fe1f8ecb3d369d8956a61fee854f97;hb=HEAD

http://wiki.openwrt.org/OpenWrtDocs/Hardware/Mikrotik/RB532

http://forum.openwrt.org/viewtopic.php?pid=43146

fetch the OpenWRT buildroot svn co https://svn.openwrt.org/openwrt/trunk/

Router 3 port ethernet
coming soon