BeagleBoard/GSoC/2021 Proposal/OmkarBhilare

=Proposal for Beaglewire Software= About Student: Omkar Bhilare Mentors: Michael Welling Proposal:BeagleWire Software Code: BeagleWire Code Wiki: BeagleWire Software GSoC: BeagleWire GSoC Project

=Status= This project is Selected for GSoC 2021. Logs can be found here: https://ombhilare999.github.io/GSoC-2021/

=Proposal=
 * Completed All the requirements listed on the ideas page.
 * The PR request for cross-compilation task: #154.

About you
IRC: Omkar Bhilare [@ombhilare99:matrix.org] Github: ombhilare999 School: Veermata Jijabai Technological Institute Country: India Primary language : English, Hindi, Marathi Typical work hours: 10AM-8PM Indian Standard Time Previous GSoC participation: This is my first time applying for GSoC, I'm an Electronics enthusiast and have a great interest in fields like FPGA, Digital VLSI, Computer Architecture. I have experienced with Intel's Quartus, Xilinx's vivado, and opensource toolchains for ice40. I have also done many projects related to Cyclone2, Upduino3.0(ICE40), Sipeed Tang Primer FPGA.

About your project

 * Project name: Beaglewire Software

Introduction
The BeagleWire is an FPGA development platform that has been designed for use with BeagleBone boards. BeagleWire is a cape on which there is an FPGA device (Lattice iCE40HX). The software support for BeagleWire is still in the development phase. In this project, I'm developing and testing the existing software support of Beaglewire. The known primary issue in Beaglewire is the interface between 32MB SDRAM and ICE40HX4K. For this Solution, I'm going to try options like LiteDRAM(a small footprint and configurable DRAM core) or Advanced SDRAM controller provided by LATTICE.

Why LiteDRAM for SDRAM Control
The Core produced by LiteDRAM is 1. Fully pipelined, high performance. 2. Configurable commands depth on bankmachines. 3. Auto-Precharge. 4. Periodic refresh/ZQ short calibration (up to 8 postponed refreshes). (LiteDRAM is already used in commercial and open-source designs)

Testing and Improvement of Subsystem Like I2C, SPI, PWM, UART
In this project I'm going to test all the subsystems like I2C, SPI, PWM, UART in Hardware and the primary goal will be to debug the issues related to it and fix them accordingly. Along with the driver code ready to use solutions will be added in software support.
 * I2C: There are two grove Connectors on BeagleWire for I2C, I will test the current Verilog Code of I2C in hardware, and will found out if further improvements can be done or not.
 * UART: The existing code of Uart will be tested in hardware, and few examples also will be added for UART.
 * PWM: New Example will be created for testing of PWM. Servo Code will serve the purpose of testing the PWM drivers.

Others

 * There are current Issues open on BeagleWire Repository, These will be solved during this project.
 * More PMODs will be interfaced with the BeagleWire.
 * Increase the Documentation and also add getting started guide for BeagleWire.

Details of Implementation
The steps give on Quick Start Guide:
 * First of all, I need to load a pre-prepared BBB image to beagle with existing all required drivers and scripts to start BeagleWire development.
 * To generate the bitstream I'm going to first try the existing fpga-load script which leverages the FPGA manager, which is the core that exports a set of functions for programming an FPGA with an Image.

LiteDRAM
1. LiteDRAM provides a small footprint and configurable DRAM core. The configuration of LiteDRAM can be changed using yml input. The examples given the repository as follows:


 * 1) This file is part of LiteDRAM.
 * 2) Copyright (c) 2018-2019 Florent Kermarrec 
 * 3) SPDX-License-Identifier: BSD-2-Clause
 * 1) Copyright (c) 2018-2019 Florent Kermarrec 
 * 2) SPDX-License-Identifier: BSD-2-Clause

{   # General -- "cpu":       "vexriscv",  # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -1,         # FPGA speedgrade "memtype":   "DDR2",      # DRAM type . ..

2. This configuration can be changed for this application that is memory type to SDRAM and CPU None: cpu=None

Testing of Subsystems
1. For this I need to synthesize the Verilog code first using IceStorm Toolchains, I will be first referring to the steps mentioned in the BeagleWire Documentation: Synthesizing Verilog Code using Icestorm Toolchains 2. Using this I can test the driver codes in hardware and observe the waveforms on DSO if needed.

PMOD Support
1. The BeagleWire has the PMOD connectors reversed from the "Standard" template. The standard template is as follows: 3.3V | GND | 3 | 2 | 1 | 0 3.3V | GND | 7 | 6 | 5 | 4

The pinout for BeagleWire PMOD: 4 | 5 | 6 | 7 | GND | 3.3V 0 | 1 | 2 | 3 | GND | 3.3V 2. So to use PMODs with BeagleWire One needs to connect the PMOD upside down or use some sort of Breakout Board. I found this Breakout made out especially for BeagleWire: BeagleWire to PMOD 3. Using this Breakout board I will be Interfacing New PMODs to BeagleWire, changes will be done in the current pcf file for GPIO position if found wrong.

Hardware Needed

 * 1) BeagleWire
 * 2) BeagleBone Black / BeagleBone Black Wireless
 * 3) Various PMODs
 * 4) PMOD Breakout Board

Experience and approach
More projects done by me can be found on my github
 * I'm well experienced with Verilog and C. I have actual experience with working with FPGAs. I have worked with Intel's Cyclone2, Sipeed's Tang primer, and Upduino3.0(ICE40) FPGA Boards.
 * I have done several projects related to these boards with Verilog some of them are as follows:
 * 1) riscv-core in verilog
 * 2) VGA Interface With Tang Primer FPGA
 * 3) Seven Segment Interface with Tang Primer FPGA
 * I have also designed various double-sided boards using Autodesk Eagle and Kicad.
 * Esp32 Development Board designed for Embedded and Robotics Application: Design, This is the last Board I had designed, this shows that I have a very good understanding of reading schematics which was one of the requirements of the project

Contingency
if I get stuck on my project and my mentor isn’t around, I will use the following resources:
 * 1) Getting Started Guide for BeagleBone by derek molloy: http://derekmolloy.ie/beaglebone
 * Current Github Repos:
 * 1) https://github.com/pmezydlo/BeagleWire
 * 2) https://github.com/mwelling/BeagleWire
 * 3) https://github.com/osresearch/BeagleWire
 * Documentation on the pmezydlo repo of BeagleWire: Documentation
 * BeagleWire Page

Benefit
''The completed project will provide the BeagleBoard.org community with easy to implement and powerful tools for the realization of projects based on Programmable Logic Device(FPGA), which will surely increase the number of applications based on it. The developed software will be easy and, at the same time, efficient tool for communication with FPGA. At this point, FPGA will be able to meet the requirements of even more advanced applications. The BeagleWire creates a powerful and versatile digital cape for users to create their imaginative digital designs.''