Ti AM33XX PRUSSv2

The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O. These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.

PRUs are programmed in Assembly, with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200Mhz, a single cycle will always take 5ns (nanoseconds) to execute.

Available PRU Resources
Click here for a full list of register mappings.

Per PRU

 * 8KB program memory
 * Memory used to store instructions and static data AKA Instruction Memory (IRAM). This is the memory in which PRU programs are loaded.


 * Enhanced GPIO (EGPIO)
 * High-speed direct access to 16 general purpose output and 17 general purpose input pins for each PRU.
 * PRU0
 * pr1_pru_0_pru_r30[15:0] (PRU0 Register R30 Outputs)
 * pr1_pru_0_pru_r31[16:0] (PRU0 Register R31 Inputs)
 * PRU1
 * pr1_pru_1_pru_r30[15:0] (PRU1 Register R30 Outputs)
 * pr1_pru_1_pru_r31[16:0] (PRU1 Register R31 Inputs)
 * various caputure modes


 * A 32-bit multiply and accumulate unit (MAC)
 * Enables single-cycle integer multiplications with a 64-bit overflow (useful for decimal results).


 * 8KB data memory
 * Memory used to store dynamic data. Is accessed over the 32-bit bus and so not single-cycle.
 * One PRU may access the memory of another for passing information but it is recommend to use scratch pad or shared memory, see below.

Shared Between PRUs

 * Scratch pad
 * 3 banks of 30 32-bit registers (total 90 32-bit registers).
 * Single-cycle access, can be accessed from either PRU for data sharing and signalling or for individual use.


 * 12KB data memory
 * Accessed over the 32-but bus, not single-cycle.