Tests:SDIO-H3-Voltage-Switching

This document describes how to test voltage switching of SDHI pins on a R-Car H3 using a Salvator-X board.

Kernel branch
The patches are included in renesas-drivers starting with renesas-drivers-2016-06-07-v4.7-rc2. They are expected to land upstream with v4.8.

Preparations
Only  and   from busybox are needed for these tests. debugfs should be activated in the kernel config.

Check default setting with no cards inserted
Here, signal voltage is reported as 3.3V for both slots:

clock:		0 Hz vdd:		0 (invalid) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	0 (off) bus width:	0 (1 bits) timing spec:	0 (legacy) signal voltage:	0 (3.30 V) driver type:	0 (driver type B) clock:		0 Hz vdd:		0 (invalid) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	0 (off) bus width:	0 (1 bits) timing spec:	0 (legacy) signal voltage:	0 (3.30 V) driver type:	0 (driver type B)
 * 1) cat /sys/kernel/debug/mmc?/ios

The POCCTRL register reports also 3.3V for SD0 and SD2. Note: The eMMC pins are already initialized for 1.8V:

0x3FF8003F
 * 1) devmem 0xe6060380

Check settings with UHS card inserted into SD0
Signal voltage of the first entry changed to 1.8V:

clock:		49999998 Hz vdd:		21 (3.3 ~ 3.4 V) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	2 (on) bus width:	2 (4 bits) timing spec:	5 (sd uhs SDR50) signal voltage:	1 (1.80 V) driver type:	0 (driver type B) clock:		0 Hz vdd:		0 (invalid) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	0 (off) bus width:	0 (1 bits) timing spec:	0 (legacy) signal voltage:	0 (3.30 V) driver type:	0 (driver type B)
 * 1) cat /sys/kernel/debug/mmc?/ios

SD0 bits of POCCTRL also changed:

0x3FF80000
 * 1) devmem 0xe6060380

Check settings with UHS card inserted into SD2
Signal voltage of the second entry changed to 1.8V:

clock:		0 Hz vdd:		0 (invalid) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	0 (off) bus width:	0 (1 bits) timing spec:	0 (legacy) signal voltage:	1 (1.80 V) driver type:	0 (driver type B) clock:		99999996 Hz vdd:		21 (3.3 ~ 3.4 V) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	2 (on) bus width:	2 (4 bits) timing spec:	5 (sd uhs SDR50) signal voltage:	1 (1.80 V) driver type:	0 (driver type B)
 * 1) cat /sys/kernel/debug/mmc?/ios

SD2 bits of POCCTRL also changed: 0x3E000000
 * 1) devmem 0xe6060380

Check settings with non-UHS card inserted into SD0
Signal voltage of the first entry changed back to 3.3V:

clock:		49999998 Hz vdd:		21 (3.3 ~ 3.4 V) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	2 (on) bus width:	2 (4 bits) timing spec:	2 (sd high-speed) signal voltage:	0 (3.30 V) driver type:	0 (driver type B) clock:		0 Hz vdd:		0 (invalid) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	0 (off) bus width:	0 (1 bits) timing spec:	0 (legacy) signal voltage:	1 (1.80 V) driver type:	0 (driver type B)
 * 1) cat /sys/kernel/debug/mmc?/ios

SD0 bits of POCCTRL also changed back:

0x3E00003F
 * 1) devmem 0xe6060380

Check settings with non-UHS card inserted into SD2
Signal voltage of the first entry changed back to 3.3V:

clock:		0 Hz vdd:		0 (invalid) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	0 (off) bus width:	0 (1 bits) timing spec:	0 (legacy) signal voltage:	0 (3.30 V) driver type:	0 (driver type B) clock:		50000000 Hz vdd:		21 (3.3 ~ 3.4 V) bus mode:	2 (push-pull) chip select:	0 (don't care) power mode:	2 (on) bus width:	2 (4 bits) timing spec:	2 (sd high-speed) signal voltage:	0 (3.30 V) driver type:	0 (driver type B)
 * 1) cat /sys/kernel/debug/mmc?/ios

SD2 bits of POCCTRL also changed back:

0x3FF8003F
 * 1) devmem 0xe6060380