BeagleBoard/GSoC/2021 Proposal/OmkarBhilare

=Proposal for Beaglewire Software Support= About Student: Omkar Bhilare Mentors: Michael Welling Code: gsoc-application Wiki: https://elinux.org/BeagleBoard/GSoC/2021_Proposal/OmkarBhilare GSoC: GSoC entry

=Status= This project is currently just a proposal.

=Proposal= Completed All the requirements listed on the ideas page. The PR request for cross-compilation task: #154.

About you
IRC: Omkar Bhilare Github: ombhilare999 School: Veermata Jijabai Technological Institute Country: India Primary language : English, Hindi, Marathi Typical work hours: 10AM-8PM Indian Standard Time Previous GSoC participation: This is my first time applying for GSoC, I'm an Electronics enthusiast and have a great interest in fields like FPGA, Digital VLSI, Computer Architecture. I have experienced with Intel's Quartus, Xilinx's vivado, and opensource toolchains for ice40. I have also done many projects related to Cyclone2, Upduino3.0(ICE40), Sipeed Tang Primer FPGA.

About your project
Project name: Beaglewire Software Support

Description
The BeagleWire is an FPGA development platform that has been designed for use with BeagleBone boards. BeagleWire is a cape on which there is an FPGA device (Lattice iCE40HX). The software support for BeagleWire is still in the development phase. In this project, I'm developing and testing the existing software support of Beaglewire. The known primary issue in Beaglewire is the interface between 32MB SDRAM and ICE40HX4K. For this Solution, I'm going to try options like LiteDRAM(a small footprint and configurable DRAM core) or Advanced SDRAM controller provided by LATTICE.
 * Introduction


 * Why LiteDRAM for SDRAM Control:

The Core produced by LiteDRAM is 1. Fully pipelined, high performance. 2. Configurable commands depth on bankmachines. 3. Auto-Precharge. 4. Periodic refresh/ZQ short calibration (up to 8 postponed refreshes).
 * LiteDRAM is already used in commercial and open-source designs


 * Testing and Improvement of Subsystem Like I2C, SPI, PWM, UART:

In this project I'm going to test all the subsystems like I2C, SPI, PWM, UART in Hardware and the primary goal will be to debug the issues related to it and fix them accordingly. Along with the driver code ready to use solutions will be added in software support.
 * I2C: There are two grove Connectors on BeagleWire for I2C, I will test the current Verilog Code of I2C in hardware, and will found out if further improvements can be done or not.
 * UART: The existing code of Uart will be tested in hardware, and few examples also will be added for UART.
 * PWM: New Example will be created for testing of PWM. Servo Code will serve the purpose of testing the PWM drivers.


 * Others:
 * There are current Issues open on BeagleWire Repository, These will be solved during this project.
 * More PMODs will be interfaced with the BeagleWire.
 * Increase the Documentation and also add getting started guide for BeagleWire.

Details of Implementation
The steps give on Quick Start Guide: 1. LiteDRAM provides a small footprint and configurable DRAM core. The configuration of LiteDRAM can be changed using yml input. The examples given the repository as follows:
 * First of all, I need to load a pre-prepared BBB image to beagle with existing all required drivers and scripts to start BeagleWire development.
 * To generate the bitstream I'm going to first try the existing fpga-load script which leverages the FPGA manager, which is the core that exports a set of functions for programming an FPGA with an Image.
 * LiteDRAM:


 * 1) This file is part of LiteDRAM.
 * 2) Copyright (c) 2018-2019 Florent Kermarrec 
 * 3) SPDX-License-Identifier: BSD-2-Clause
 * 1) Copyright (c) 2018-2019 Florent Kermarrec 
 * 2) SPDX-License-Identifier: BSD-2-Clause

{   # General -- "cpu":       "vexriscv",  # Type of CPU used for init/calib (vexriscv, lm32) "speedgrade": -1,         # FPGA speedgrade "memtype":   "DDR2",      # DRAM type . ..

2. This configuration can be changed for this application that is memory type to SDRAM and CPU None: cpu=None

1. For this I need to synthesize the Verilog code first using IceStorm Toolchains, I will be first referring to the steps mentioned in the BeagleWire Documentation: Synthesizing Verilog Code using Icestorm Toolchains 2. Using this I can test the driver codes in hardware and observe the waveforms on DSO if needed.
 * Testing of Subsystems like I2C, UART, PWM, and SPI:

Timeline
Provide a development timeline with a milestone each of the 11 weeks and any pre-work. (A realistic timeline is critical to our selection process.)

Experience and approach
Esp32 Development Board designed for Embedded and Robotics Application: Design, This is the last Board I had designed, this shows that I have a very good understanding of reading schematics which was one of the requirements of the project
 * I'm well experienced with Verilog and C. I have actual experience with working with FPGAs. I have worked with Intel's Cyclone2, Sipeed's Tang primer, and Upduino3.0(ICE40) FPGA Boards.
 * I have done several projects related to these boards with Verilog some of them are as follows:
 * 1) riscv-core in verilog
 * 2) VGA Interface With Tang Primer FPGA
 * 3) Seven Segment Interface with Tang Primer FPGA
 * 4) and many more projects done by me can be found on my github
 * I have also designed various double-sided boards using Autodesk Eagle and Kicad.

Contingency
What will you do if you get stuck on your project and your mentor isn’t around?

Benefit
If successfully completed, what will its impact be on the BeagleBoard.org community? Include quotes from BeagleBoard.org community members who can be found on http://beagleboard.org/discuss and http://bbb.io/gsocchat.

Misc
Please complete the requirements listed on the ideas page. Provide link to pull request.

Suggestions
Is there anything else we should have asked you?