BeagleBoardJTAG

The BeagleBoard comes with a 14 pin TI JTAG connector. For JTAG pin out see section 8.17 of BeagleBoard HW Reference Manual (rev. A5). This is the same header interface as used in other TI products and is NOT the standard 14 pin ARM layout. Depending on your JTAG tool, you'd need a 20-pin to 14-pin TI adapter.

The 14-pin TI JTAG connector that is used on BeagleBoard is supported by a large number of JTAG emulation products and has been tested using Lauterbach, Spectrum Digital XDS510USB+ and TI XDS560 emulation pods. Note that it will not work with the Spectrum Digital XDS510USB (non-plus) as it does not support a target with 1.8V JTAG.

[[media:flyswatter-ti-jtag.pdf|HERE]] is a verified schematic for a JTAG adapter from TinCanTools

This is the unverified TI JTAG pin-out

JTAG_TMS   1 -  - 2  JTAG_nTRST JTAG_TDI   3 -  - 4  GND VREF       5 -  x 6  KEY (empty) JTAG_TDO   7 -  - 8  GND JTAG_RTCK  9 -  - 10 GND JTAG_TCK  11 -  - 12 GND JTAG_EMU0 13 -  - 14 JTAG_EMU1

Note: JTAG on BeagleBoard uses 1.8V!

Open source
It would be very interesting to get the JTAG working with open source tools.

OpenOCD JTAG bring up

On IRC it was discussed what will be necessary to get OpenOCD working with OMAP3 on BeagleBoard:


 * OpenOCD compatible JTAG hardware interface with FTDI's FT2232 chip, e.g. Flyswatter.
 * Create an adapter to convert the Flyswatter 14-pins JTAG into 14-pins TI JTAG
 * Get latest OpenOCD source
 * Add Cortex-A8 CPU ID. Currently only Cortex-M3 is supported. Take this as example. Once you connect to target you should get error message expect cpuid of xxxxxx but got yyyyyy which should contain Cortex-A8 CPU ID.
 * Take CPU scan lengths from OMAP3530 CCS config.
 * Regarding EMU0/EMU1 pins on BeagleBoard, pulling both pins down does currently not have the desired effect (the device hangs as if the adapter was configured to halt on reset and only one TAP is visible. Therefore OpenOCD will not be able to validate the scan chain. The documentation for the control of EMU0/EMU1 is very misleading:

0 0 ICEPick + default TAP(s) 0 1 ICEPick Reserved 1 0 ICEPick Wait-in-reset 1 1 ICEPick Default condition NOTES: ICEPick is always in the scan chain Default TAPs are the ARM and the ETB

This table is identical to the Davinci documentation, with one BIG difference, the OMAP3530 has NO ARM or ETB taps which means that the configuration of EMU0-L/EMU1-L basically cases the system to halt. Per TI documentation, OpenOCD is considered 3rd party and has no relationship with TI through the SDO Emulation Developer Community, it will need to use the EMU0-H/EMU1-H configuration. Because the OMAP3530 uses a TAP router, it needs to be programmed with the information about available TAPS. Once the DAP has been added to the TAP router, via a programming sequence, the ARM core can be accessed.

TI has a good presentation describing the functionality of the ICEPick TAP Router (or generically refered to as JTAG Route Controller or JRC). The ICEPick jtag device ID is 0x0b73b02f (Manufacturer: 0x017, Part: 0xb73b, Version: 0x0) and is the same as the Davinci series.

It may still be possible to use the EMU0-L/EMU1-L configuration, but with consideration that the TAP router will already configured for with the arm core interface. Yet to be tested,

If above basics work, additionally MMU, cache support and some include files for A8 might be added to OpenOCD.

Note: If you made some progress regarding BeagleBoard OpenOCD support, please send a short note to BeagleBoard ML.

Creating an adapter
The Flyswatter we plan to use has a 14 pin ARM layout, so we need to create a converter. From JTAG pin assignments document:

    ARM-14-JTAG                               TI-14-JTAG VREF       1 - - 2  GND           JTAG_TMS    1 -  - 2  JTAG_nTRST JTAG_nTRST 3 - - 4  GND           JTAG_TDI    3 -  - 4  GND JTAG_TDI   5 - - 6  GND           VREF        5 -  x 6  KEY (empty) JTAG_TMS   7 - - 8  GND           JTAG_TDO    7 -  - 8  GND JTAG_TCK   9 - - 10 GND           JTAG_RTCK   9 -  - 10 GND JTAG_TDO  11 - - 12 JTAG_SRST_N   JTAG_TCK   11 -  - 12 GND VREF      13 - - 14 GND           JTAG_EMU0  13 -  - 14 JTAG_EMU1 FlySwatter               TOP               Beagle

Unverified wireing diagram between the TinCan Tools Flyswatter and the OMAP3 Beagle Board.

Nishanth Menon did an adapter and added some explanation.

BDI 2000
Chuck Fleming reports:

The BDI2000 appears to work with the omap35xx.cfg and regOMAP3500.def files that come with the BDI hardware. I had to modify the 10-pin cable so that the BeagleBoard JTAG header matched the BDI target A connector:

beagle>reset - TARGET: processing reset request - TARGET: BDI executes scan chain init string - TARGET: Bypass check 0x00000001 => 0x00000002 - TARGET: JTAG exists check passed - Core#0: ID code is 0x0B6D602F - Core#0: DP-CSW is 0xF0000000 - Core#0: DBG-AP at 0xD4011000 - Core#0: DIDR   is 0x15141012 - TARGET: BDI removes RESET - TARGET: BDI waits for RESET inactive - TARGET: Reset sequence passed - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: processing target startup passed beagle>halt Core number      : 0 Core state       : debug mode (ARM) Debug entry cause : Debug Request Current PC       : 0x40200000 Current CPSR     : 0x000001d3 (Supervisor) beagle>rdall User    FIQ     Superv   Abort     IRQ      Undef GPR00: 480029fc 480029fc 480029fc 480029fc 480029fc 480029fc GPR01: 00000000 00000000 00000000 00000000 00000000 00000000 GPR02: 00000001 00000001 00000001 00000001 00000001 00000001 GPR03: 00000060 00000060 00000060 00000060 00000060 00000060 GPR04: 00000000 00000000 00000000 00000000 00000000 00000000 GPR05: 80f2f2f4 80f2f2f4 80f2f2f4 80f2f2f4 80f2f2f4 80f2f2f4 GPR06: 80f2f2f4 80f2f2f4 80f2f2f4 80f2f2f4 80f2f2f4 80f2f2f4 GPR07: 80e9ee88 80e9ee88 80e9ee88 80e9ee88 80e9ee88 80e9ee88 GPR08: 80e3ffdc 34484608 80e3ffdc 80e3ffdc 80e3ffdc 80e3ffdc GPR09: 80e3fec8 26a1c132 80e3fec8 80e3fec8 80e3fec8 80e3fec8 GPR10: 00000018 08040f16 00000018 00000018 00000018 00000018 GPR11: 80e3fecc 3c278260 80e3fecc 80e3fecc 80e3fecc 80e3fecc GPR12: 0000006e 24200625 0000006e 0000006e 0000006e 0000006e GPR13: 00000000 00000000 80e3feb0 00000000 00000000 d1868045 GPR14: 00000000 00000000 80e84f44 00000000 00000000 d55a4cc8 PC  : 40200000 CPSR : 000001d3 SPSR :         00000000 00000000 00000000 00000000 00000000 beagle>md 0x40200000 40200000 : e320f000 e320f000 e320f000 e320f000 .. ... ... ... . 40200010 : e320f000 e320f000 e320f000 eafffffc .. ... ... ..... 40200020 : b6273502 e7aa052b 047694c8 91ca77d8 .5'.+.....v..w.. 40200030 : 12b9579e ef2eef1b 00543892 494f9bc1 .W.......8T...OI 40200040 : 3f63013d 82eee656 b7adfe8d 993f1368  =.c?V.......h.?. 40200050 : 51f1cf9b 0464a23e bea76e3c 3d275f5c ...Q>.d.<n..\_'= 40200060 : 76554290 6776c892 a6cd088f 6dd4529a .BUv..vg.....R.m 40200070 : 067261b8 e5f80e9e cb4ea075 25a9dd95  .ar.....u.N....% 40200080 : 779db8c6 0496597b 7d5f8d5a 24f44cd6 ...w{Y..Z._}.L.$ 40200090 : 99ab46f9 9ddc06d9 fd34567a 2035bab8 .F......zV4...5 402000a0 : a16b6760 fe863cf7 29046202 39fb0d49 `gk..<...b.)I..9 402000b0 : dc9fd18c e50f536c 09ae66dd cad9ff91  ....lS...f...... 402000c0 : c46bdbdb be791808 89ff83fa 2d3bc71e  ..k...y.......;- 402000d0 : 43f5a3b6 0aed1747 ba3c4752 6af0573a  ...CG...RG<.:W.j 402000e0 : 3570da77 9a1dc961 324b876c 5d592060  w.p5a...l.K2` Y] 402000f0 : b870f487 1277c035 4609dcf4 53b534c4  ..p.5.w....F.4.S beagle>ti      Core number       : 0      Core state        : debug mode (ARM)      Debug entry cause : Single Step      Current PC        : 0x40200004      Current CPSR      : 0x000001d3 (Supervisor) beagle>ti      Core number       : 0      Core state        : debug mode (ARM)      Debug entry cause : Single Step      Current PC        : 0x40200008      Current CPSR      : 0x000001d3 (Supervisor) beagle>

BDI config
The BDI config files might help getting OpenOCD to work with BeagleBoard.

This configuration assumes the "default" EMU 0 and 1 configuration (both not connected/high state). In this EM setup at first only one TAP is exported. A set of commands must be run on the first tap (embedded ICE) to enable access to the core:

SCANINIT   t1:w1000:t0:w1000:  ;toggle TRST, SCANINIT   ch10:w1000:         ;clock TCK with TMS high and wait SCANINIT   i6=07:d8=89:i6=02:  ;connect and select router SCANINIT   d32=81000080:       ;IP control: KeepPowered SCANINIT   d32=a3002048:       ;TAP3: DebugConnect, ForcePower, ForceActive SCANINIT   d32=81000081:       ;IP control: KeepPowered, SysReset SCANINIT   d32=a3002148:       ;enable TAP3 SCANINIT   cl10:i10=ffff       ;clock 10 times in RTI, scan bypass