The download and simulation problems of MYC-C7Z010/20 JTAG and the solutions

=Overview= The MYD-C7Z010/20 development board designed by MYIR Tech Limited takes full features of the Zynq-7010 / 7020 SoC which is among the Xilinx Zynq-7000 family, featuring powerful dual-core ARM Cortex-A9 processing system and Xilinx 7-series Field Programmable Gate Array (FPGA) logic unit to create a rich set of peripherals to the base board through headers and connectors including one RS232 port, four USB Host ports, one Gigabit Ethernet port, CAN, HDMI, LCD/Touch screen, TF card slot, RTC, one XADC header to allow you to take advantage of Xilinx XADC; it has three PMoD headers to meet your I/O needs with PMoDs (only for 7020); it also has a low-pin count FMC connector to allow various FMC cards for custom I/O options. User can integrate a MYC-C7Z010 or a MYC-C7Z020 SOM on the same base board, thus making two variants of Zynq evaluation boards.

=Bootmode= The boot mode of ZYNQ 7000 is up to MIO[5-2]. MIO[5-3] must be 0 when you choose boot from JTAG. MIO2 determines the mode of JTAG. First we shall explain how to enable JTAG port. Regarding the difference between Cascade mode and Independent mode of JTAG, it is important to know that ZYNQ 7000 has 2 debugging related ports, namely DAP and TAP.



TAP is on the PL end, DAP is on the PS end. The JTAG port provided by MYIR’s development board is connected to PL_JTAG, so you must use Cascade mode if you need access to the DAP on the PS end.

=How to enable JTAG= The simplest way to enable JTAG port: choose JTAG boot which is to pull down MIO[5-3], then power-on again to enter JTAG boot mode, the JTAG port is enabled at this moment. It is important to note that after the boot mode is changed, the power-on again must be done in order to make boot mode change take effect. Because ZYNQ 7000 only collect boot mode pin from the sample at the time of electrical reset.

If it is not in JTAG boot mode, whether JTAG is enabled or not depends on the current security mode of ZYNQ. If ZYNQ boots in secure boot mode, ZYNQ chip will ban JTAG port, making it impossible to download or debug via JTAG port. If ZYNQ boots in non-secure mode, the JTAG port is enabled. So we need to make ZYNQ boot in non-secure mode to enable JTAG port. In order to make ZYNQ boot in non-secure mode, you need to type 0xA5C3C5A3 or 0x3A5C3C5A in the Encrypted status field of BootRom Header. This involves the fabrication of FSBL which won’t be expanded on here.

=The JTAG boot mode of MYC-C7Z010/20= MYC-C7Z010/20 provide 2 boot modes, SD card boot mode and QSPI boot mode. What about JTAG boot mode? Sorry, we pull up MIO5 in our CPU module when we design it, because of consideration for some reasons and the convenience to switch between SD card boot mode and QSPI boot mode. But there are other ways to do this, which is to set FSBL to non-boot mode, then the JTAG port is accessible. So we need to make a non-boot mode FSBL if we want to use JTAG on MYC-C7Z010/20. We can download and debug other applications via the JTAG port after the FSBL runs.

=The required conditions to use JTAG to download and debug= 1.	Make the FSBL of non-secure mode, you can only choose to make the FSBL of SD card.

2.	Choose to boot from SD card.

3.	Power up again, JTAG enabled.

=Note= 1.	JTAG port is prohibited if a valid FSBL is not found in the SD card or QSPI boot device when ZYNQ is booting.

2.	Must power-up again after changing the boot mode.

3.	If the Linux system in the SD card is started, the JTAG port shouldn’t be accessed because the MMU has started at this time and the access will lead to MMU error.

=Solutions= There is no FSBL in the helloworld of example projects of MYD-C7Z010/20 CD, so we need the aid of the project of EMIO in the Z-turn experiment.

You can download it here for 7Z010 chip.

You can download it here for 7Z020 chip.

Download, unzip, then copy the BOOT.bin file to a bootable TF card.

Use the boot jumper on the development board in TF card mode, connect JTAG, supply power to the development board. This bin file is copied from Z-turn board and the ports are different so no information can be seen via the serial port, we just use it to set and enter the non-secure mode and that purpose has been achieved. Now connect the development board and work with Vivado SDK. Note: the jumper to enable watchdog on the development board must be “disconnected”.

=Appendix= BOOT.bin configuration diagram of CPU module: