CI20 Hardware

This page details the technical specifications and components of the MIPS Creator CI20 development board.

Power
The power connector is a 5V 4mm (shield) x 1.7mm (pin) center positive connector. It takes 5V only. Note that this connection is identical to that of the original Sony PSP, so power cables intended for that console also work for the CI20.

HDMI
Full sized HDMI connection with audio out support as well. The HDMI block on the JZ4780 supports HDMI v1.4a.

USB A connector (left)
Paralleled with the mini-OTG connector.

USB A connector (right)
Connected to the EHCI USB controller in the SoC.

USB mini-OTG connector
Is paralleled with the left hand USB A connector - do not plug into both of these at once. Has the OTG VBUS controlled by the jumper next to it.

OTG VBUS jumper
Controls the VBUS for the OTG ports - would somebody like to describe the difference between having the connector fitted or not please.

Ethernet
10/100 RJ45, connects to the DM9000 chipset.

Audio
Standard 4-pin headset connector, with auto OMTP/CTIA detection (so should work with any standard 4-pin headset).

Button
The button between HDMI and Ethernet is not a reset button.

It is boot_select0. Combined with JP3, it can be used to boot the CI20 from the USB.

It can also be used as a gpio once the CI20 is powered up. The boot_sel0 pin is connected to.

Pinmux options can be checked to see which gpio is in kernel you booted.

In the 3.15 kernel, the gpio is number 113.

You can export the gpio via

echo 113 > /sys/class/gpio/export

And then use it.

Boot mode selector
See the silkscreen on the board and the section at the end of the JZ4780 programmers manual. Fundamentally you can boot from the on-board NAND or direct off the SDcard without having to press the button during boot. There is also a USB boot function available, but it is not a standard DFU type boot, and requires JZ4780 specific host support.

SDcard
Standard pinout full sized SD/MMC slot. Can be used for direct booting, or for bulk storage (standard MTD support under Linux). Is wired to the MSC0 block in the SoC.

Camera
The camera connector is 24 pin (26 pins on the schematic - two of which are the side ground solder tabs on the connector itself - the actual cable interface is 24 pin), and CMOS DVP 8-bit camera compatible. The Omnivision OV5640 5Mpixel unit can be used with the CI20 (often labelled FD5640 on the actual part)

Note Be aware that there are some SMT components directly under where the camera unit sits. If your camera unit has a conductive rear surface then this may short out on the board. Symptoms we have seen include board resets. Please insulate the area either on the PCB or the back of the camera unit to avoid this.

IR
The CI20 has an infrared remote control receiver (part IRM-2638A, carrier frequency 37.9kHz), which is connected to GPIO for software decoding.

LED
The CI20 board features a dual colour red & blue LED. It is controlled by GPIO, which also controls the USB VBUS supply. When is high the LED lights red, when  is low it lights blue. Software cannot power off the LED. A simple way to toggle the LED colour is to write to the PFPAT0S & PFPAT0C registers from the U-boot shell, in order to toggle the GPIO. The following example will toggle the colours rapidly, leading to the LED appearing purple:

while true; do mw.l 0xb0010548 0x8000; mw.l 0xb0010544 0x8000; done

Dedicated UART header
Pinout and other functions of the dedicated UART header. This is uart4 of the SoC. Note that uart0 is on the 26pin main expansion header.

Primary expansion header
Pinout diagram for the main CI20 0.1" pitch 26 pin header


 * 1) Note that the PWM facility is unavailable as this PWM unit is used by the Linux kernel SMP timer code
 * 2) Note that the GPS interface is unavailable as it is (believed to be) electrically incompliant
 * 3) Note that the I2S block is not useable on the header as not all I2S pins are brought out

Secondary expansion header
Pinout diagram for the secondary CI20 0.1" pitch 16 pin header

EJTAG
14-pin MIPS EJTAG headers. See proposed OpenOCD/wiggler support project.


 * 1) Note that the JTAG function is controlled by, and may be turned on by the bootloader - see the JZ4780 Programmers Manual

SoC
Is an Ingenic JZ4780 - see the data sheet and programmers manuals referenced on this page.

DDR/RAM
Comprises of four H5TQ2G83DFR-H9C 2Gbit DDR3 chips, providing 8 bits of data each, providing a 32bit DDR3 memory bus to the SoC. Anybody have details of the standard clock rate?

ROM/NAND
Is provided by a single Samsung K9GBG08UOA NAND flash, using an 8bit data interface to the SoC.

Ethernet
Is provided by a Davicom DM9000C connected vi an 8-bit interface to the SoC, providing 10/100 ethernet.

WiFi/BT
Is provided by an Ingenic IW8103, based on a Broadcom 4330, connected via SDIO to the SoC MSC1 port.

PMU
Is an Active-Semi ACT8600 specifically designed for the Ingenic JZ family of SoCs.

RTC
Is provided by a Pericom PT7C4337UE connected to the SoC via the I2C_4 bus.

Microphone switcher
The automatic 4-pin microphone switching/detection is provided by a Fairchild FSA8049 audio jack detection device.

Test Points
Description of the (rather small little silver dot) test points on the board, derived from the schematic.

OTP and MAC address formats
The following data is stored in the JZ4780 OTP ROM/efuse. This data can be accessed from Linux via the sysfs path of /sys/devices/platform/jz4780-efuse/

The C definition of the actual efuse area data format is: struct __packed__ otp { uint32 serial_number; /* As a decimal, huge range */ uint32 date; /* ISO8601 yyyymmdd format-ish as an int – for instance ‘20140527’d for May 27th 2014 */ char manufacturer[2]; /* ascii 2-character encoding of manufacturer – ‘NP’ == Nopa */ unsigned char mac[6]; /* six byte/48bit MAC address stored as 8-bit integers */ };