CI20 HW test

Testing the ci20 GPIO ports
A quick comprehensive way to test the 2 GPIO ports of the ci20 is to connect it directly to a second ci20 board via IDC ribbon cables. Because of the 1 to 1 connection between the ports all supply and ground pins are connected directly to the correct voltage on the corresponding board and all GPIO functions are controlled and monitored by the same pin on the ci20 board which is running the tests. In addition to the 2 ports the test system described here required the UART ports of the dedicated UART header to be connected to allow commands and data to be transferred between the 2 units.

Powering the test system
Ci20 board power requirements measured at the 5V jack plug

Note USB keyboard mouse and HDMI monitor add about 100mA

Test description
The test is designed to be fully automatic and repeatable at any time in the future. This will enable any tested boards be compared against previous reports in order to diagnose functional degradation of units returning from the field. The master or controlling board runs a script which sends a series of commands to the unit on test. These commands perform a sequence of reads and writes to each pin on the ports and confirm that the port voltage has responded accordingly.

Test pattern file
The script reads a test pattern from a file and plays it line by line into the GPIO pins. The pins of the corresponding board are then read and the results are written into a second file with the same format. The command diff will quickly highlight any discrepancies between the two files. The format of these files is as follows:

--x-x-00-0000-00-00-0000-0

--x-x-10-0000-00-00-0000-0

--x-x-01-0000-00-00-0000-0

--x-x-00-1000-00-00-0000-0

Each character on the line represents the pin number on the port 0 is low and 1 high. Any pins not included in the test are marked with an 'x'. Power and ground pins are represented with a -.

Running the port test on ci20 dev board.
This software is designed to test a ci20 primary and secondary expansion ports The test is performed from a second ci20 board connected to the test target

Run the tests by executing the following steps:
 * 1) Connect the two boards expansion ports with an IDC ribbon cables. Ensuring a 1 to 1 connection
 * 2) Connect the two boards serial ports for the comms (ttyS4) TX->RX & RX->TX
 * 3) Login to the test target and set the ttyS4 port (see below). Start bash with io redirected to ttyS4
 * 4) Login to the testing ci20 and set the ttyS4 port. Run the genrep.sh script

Set up serial comms between the two ci20 boards
Set comms serial ports on both boards with the following commands

$ sleep 99999 > /dev/ttyS4 &      # keeps the port open $ stty < /dev/ttyS4 115200 raw $ stty < /dev/ttyS4 -echo -echok -echoe $ stty < /dev/ttyS4 nl

Test the comms link with the following commands

$ cat /dev/ttyS4 & $ echo ls > /dev/ttyS4

You should see the output from the ls command which ran on the remote ci20. After testing the comms don't forget to "kill the cat".

Software download
The software is located on github here.

Images of test setup
Two ci20 boards connected for testing with IDC ribbon cables. The orange and white cables are the TX and RX comm port wires



Two ci20 boards connected for test with logicport monitoring signals



Logicport waveforms of a test pattern running



Example of output file
Test report for ci20 id 0000052c generated on : Thu Sep 18 11:54:52 BST 2014 Primry expansion header diff between test pattern and received data for port read +++++++++++ +++++++++++ diff between test pattern and received data for port write +++++++++++ +++++++++++ Secondard expansion header diff between test pattern and received data for port read +++++++++++ +++++++++++ diff between test pattern and received data for port write +++++++++++ +++++++++++ TEST PASSED all port reads/writes match

Example of output file with -v option
Test report for ci20 id 0000052c generated on : Thu Sep 18 11:55:27 BST 2014 Primry expansion header --x-x-00-0000-00-00-0000-0 --x-x-10-0000-00-00-0000-0 --x-x-01-0000-00-00-0000-0 --x-x-00-1000-00-00-0000-0 --x-x-00-0100-00-00-0000-0 --x-x-00-0010-00-00-0000-0 --x-x-00-0001-00-00-0000-0 --x-x-00-0000-10-00-0000-0 --x-x-00-0000-01-00-0000-0 --x-x-00-0000-00-10-0000-0 --x-x-00-0000-00-01-0000-0 --x-x-00-0000-00-00-1000-0 --x-x-00-0000-00-00-0100-0 --x-x-00-0000-00-00-0010-0 --x-x-00-0000-00-00-0001-0 --x-x-00-0000-00-00-0000-1 --x-x-00-0000-00-00-0000-0 --x-x-11-1111-11-11-1111-1 --x-x-01-1111-11-11-1111-1 --x-x-10-1111-11-11-1111-1 --x-x-11-0111-11-11-1111-1 --x-x-11-1011-11-11-1111-1 --x-x-11-1101-11-11-1111-1 --x-x-11-1110-11-11-1111-1 --x-x-11-1111-01-11-1111-1 --x-x-11-1111-10-11-1111-1 --x-x-11-1111-11-01-1111-1 --x-x-11-1111-11-10-1111-1 --x-x-11-1111-11-11-0111-1 --x-x-11-1111-11-11-1011-1 --x-x-11-1111-11-11-1101-1 --x-x-11-1111-11-11-1110-1 --x-x-11-1111-11-11-1111-0 --x-x-11-1111-11-11-1111-1 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-11-1111-11-11-1111-1 diff between test pattern and received data for port read +++++++++++ +++++++++++ --x-x-00-0000-00-00-0000-0 --x-x-00-0000-00-00-0000-1 --x-x-00-0000-00-00-0001-0 --x-x-00-0000-00-00-0010-0 --x-x-00-0000-00-00-0100-0 --x-x-00-0000-00-00-1000-0 --x-x-00-0000-00-01-0000-0 --x-x-00-0000-00-10-0000-0 --x-x-00-0000-01-00-0000-0 --x-x-00-0000-10-00-0000-0 --x-x-00-0001-00-00-0000-0 --x-x-00-0010-00-00-0000-0 --x-x-00-0100-00-00-0000-0 --x-x-00-1000-00-00-0000-0 --x-x-01-0000-00-00-0000-0 --x-x-10-0000-00-00-0000-0 --x-x-00-0000-00-00-0000-0 --x-x-11-1111-11-11-1111-1 --x-x-11-1111-11-11-1111-0 --x-x-11-1111-11-11-1110-1 --x-x-11-1111-11-11-1101-1 --x-x-11-1111-11-11-1011-1 --x-x-11-1111-11-11-0111-1 --x-x-11-1111-11-10-1111-1 --x-x-11-1111-11-01-1111-1 --x-x-11-1111-10-11-1111-1 --x-x-11-1111-01-11-1111-1 --x-x-11-1110-11-11-1111-1 --x-x-11-1101-11-11-1111-1 --x-x-11-1011-11-11-1111-1 --x-x-11-0111-11-11-1111-1 --x-x-10-1111-11-11-1111-1 --x-x-01-1111-11-11-1111-1 --x-x-11-1111-11-11-1111-1 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-10-1010-10-10-1010-1 --x-x-01-0101-01-01-0101-0 --x-x-11-1111-11-11-1111-1 diff between test pattern and received data for port write +++++++++++ +++++++++++ Secondard expansion header --000000 --100000 --010000 --001000 --000100 --000010 --000001 --000000 --111111 --011111 --101111 --110111 --111011 --111101 --111110 --111111 --101010 --010101 --101010 --010101 --101010 --010101 diff between test pattern and received data for port read +++++++++++ +++++++++++ --000000 --000001 --000010 --000100 --001000 --010000 --100000 --000000 --111111 --111110 --111101 --111011 --110111 --101111 --011111 --111111 --101010 --010101 --101010 --010101 --101010 --010101 diff between test pattern and received data for port write +++++++++++ +++++++++++ TEST PASSED all port reads/writes match

HW Test