BeagleBoard/BeagleWire

BeagleWire


BeagleWire - FPGA development cape for the BeagleBone

The BeagleWire is an FPGA development platform that has been designed for use with BeagleBone boards. BeagleWire is a cape on which there is an FPGA device - Lattice iCE40HX. The Lattice iCE40 is a family of FPGAs with a minimalistic architecture and very regular structure, designed for low-cost, high-volume consumer and system applications. The significance of FPGAs is continuously increasing, as they are more and more often used to support ARM processors. BeagleWire does not require external tools (JTAG) and the whole software is Open Source. iCE40 is an energy saving device, allowing to work with small batteries. FPGA cape allows easy and low cost start for beginners who would like to take their first steps in working with FPGAs. The developed software will be an easy and, at the same time, efficient tool for communication with FPGA. At this point FPGA will be able to meet the requirements of even more advanced applications. The BeagleWire creates a powerful and versatile digital cape for users to create their imaginative digital designs.

BeagleWire features:

 * FPGA: Lattice iCE40HX4K - TQFP 144 Package
 * GPMC port access from the BeagleBone
 * SPI programming port from the BeagleBone
 * 4 layer PCB optimized design to support maximum performance for high bandwidth applications
 * BeagleBoard optimized - compatible with BeagleBone Black, BeagleBone Black Wireless, element14 BeagleBone Black Industrial
 * does not require external tools (JTAG)
 * minimalistic architecture and very regular structure
 * energy saving device allows to work with small batteries
 * lower application costs
 * fully open-source toolchain

BeagleWire Peripherals:

 * 32 MB SDRAM
 * 100Mhz external clock
 * 4 LEDs
 * 4 PMOD connectors
 * 4 Grove connectors
 * 2 user push buttons
 * 2 input DIP switch

Software\Driver support
BeagleWire software support is still developing. A lot of useful examples and ready to use solutions can be found there. For communication between FPGA and ARM, GPMC can be used. This is an easy and efficient solution. BeagleWire software repository has special components for it. You can just map your logic in BeagleBone memory. A lot of examples have kernel driver e.g. SPI, GPIO. After preparing the FPGA device you can use it as a typical GPIO/SPI from user space. A part of examples do not belong to kernel subsystems e.g. rotary excoder, ultrasonic ranger sensor or blink leds. In these examples, you can connect to FPGA using write/read operation for /dev/mem file.

Authors
The project is the result of the community work and it is still under development. If you can support this project or if you have any questions, feel free to contact us. Michael Welling mwelling@ieee.org Patryk Mezydlo mezydlo.p@gmail.com

Resources
''BeagleWire KiCAD Repository ''BeagleWire Software Repository ''BeagleWire Hackaday.io project page ''BeagleWire Hackster.io project page ''BeagleWire Schematic

GPMC Communications interface
The general-purpose memory controller (GPMC) is a unified memory controller dedicated to interfacing external memory devices: SRAM-like memories and application-specific integrated circuit (ASIC) devices, asynchronous, synchronous, and page mode (only available in non-multiplexed mode) burst NOR flash devices, NAND Flash, Pseudo-SRAM devices. The GPMC bus enables a high bandwidth interface between the FPGA and the ARM processor. GPMC controller is configured from the DTS file. GPMC pins are brought out to BeagleBone P8/P9 headers. BeagleWire software repository contains a component written in Verilog which supports communication between FPGA and ARM.

SPI Programming interface
Programming is done by SPI interface. BeagleWire uses second BeagleBone SPI port. SPI frequency should be between 1Mhz and 25Mhz.

PMOD Expansion Ports
BeagleWire contains four Digilent Inc. Pmod ports. The Pmod standard has a lot of ready modules. Thanks to four Pmod ports we can use as many as 24 additional pins.

LEDs
There are four blue LEDs.

DIP Switch
BeagleWire has two DIP switch. "ON" position is treated as logical zero.

Push Button
There are two user buttons. We used schmitt trigger, a simple structure which prevents buttons bouncing.

Additional common IRQ lines
Two lines are directly connecting BBB and BW. These lines do not have intended use. In many applications they are used as interrupt lines.

SDRAM Memory
BealgeWire has 32 MB SDRAM memory. BeagleWire software repository contains a simple SDRAM controller written in Verilog which supports communication between SDRAM and iCE40.

Grove Expansion Ports
BeagleWire contains four Grove connectors. First and second connectors are used as I2C. Other connectors have no destinations.

External clock source
BeagleWire has an external 100 Mhz clock generator. Clock speed can be changed using internal PLL.

Pinout
More information about I/O connections can be found at:BeagleWire pcf file or BeagleWire Schematic

Prepare BBB Image
Prepare custom kernel image, an easy instruction on how to do it can be found here: BBB prepare image instruction. Attach() FPGA-mgr and iCE40-spi driver. Version of linux kernel should be 4.12 or newer. Device Drivers ---> FPGA Configuration Support --->  FPGA Configuration Framework      Lattice iCE40 SPI

Writeing EEPROM configuration contents
BeagleWire cape has a EEPROM memory, so that the BBB device overlay is automatically loaded up on each boot up. EEPROM contents and loading script are located in BeagleWire software repository. Check BW_EEPROM.bin content: $ xxd BW_EEPROM.bin It should look like this: 00000000: aa55 33ee 4131 4265 6167 6c65 426f 6e65 .U3.A1BeagleBone 00000010: 2042 6561 676c 6557 6972 6543 6170 6500  BeagleWireCape. 00000020: 0000 0000 0000 3030 4130 6265 6167 6c65 ......00A0beagle 00000030: 626f 6172 642e 6f72 6700 4257 2d49 4345 board.org.BW-ICE 00000040: 3430 4361 7065 0000 0000 3030 4257 5245 40Cape....00BWRE 00000050: 5630 3230 3137 0000 0000 0000 0000 0000 V02017.......... Load EEPROM using script: $ sudo ./load_eeprom.sh

Device Tree Overlay
Device Tree is required for enabling SPI and GPMC. Install the DTS compiler: $ wget -c https://raw.githubusercontent.com/RobertCNelson/tools/master/pkgs/dtc.sh $ chmod +x dtc.sh $ ./dtc.sh Compile the dts file: $ dtc -O dtb -o DTS/BW-ICE40Cape-00A0.dtbo -b 0 -@ DTS/BW-ICE40Cape-00A0.dts Copy dtbo file to /lib/firmware on the BBB: $ cp BW-ICE40Cape-00A0.dtbo /lib/firmware

Installing the IceStorm toolchain
Install toolchain on PC or BBB. On PC: $ sudo ./install_IceStorm.sh

On BBB: $ sudo ./install_IceStorm.sh BBB

Synthesizing Verilog code using IceStorm toolchain
Prepare Verilog module for first FPGA programming top.v: module top(input clk, output [3:0] led);

reg [27:0] counter = 0; always @(posedge clk) counter <= counter + 1;

assign led[0:3] = counter[24:27]; endmodule

PCF file is used for connecting input/output module signals with physical pins in FPGA device. pinmap.pcf: set_io clk 61
 * 1) USER CLOCK

set_io led[0] 28 set_io led[1] 29 set_io led[2] 31 set_io led[3] 32
 * 1) LED

Makefile: PROJ = blink         # project name BUILD = ./out        # output directory DEVICE = 8k          # device FOOTPRNT = tq144:4k  # device package SRC = top.v          # top module name SRC +=               # additional module name PIN_SRC = pinmap.pcf # pcf file name

.PHONY: all load clean

all: mkdir -p $(BUILD) yosys -p "synth_ice40 -top top -blif $(BUILD)/$(PROJ).blif" $(SRC) arachne-pnr -d $(DEVICE) -P $(FOOTPRNT) -p $(PIN_SRC) -o $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).blif icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin echo -e "\x0\x0\x0\x0\x0\x0\x0" >> $(BUILD)/$(PROJ).bin load: dd if= $(BUILD)/$(PROJ).bin of=/dev/spidev1.0

clean: rm -rf ./$(BUILD)/

Programming the FPGA from the BeagleBone
Will be soon.

Examples
BeagleWire software repository has a lot of different sources. The following description shows how to use it. Examples can be divided into two parts. The first part is the simplest examples which do not have their own subsystem in Linux kernel e.g. rotary excoder, ultrasonic ranger sensor or blink leds. In these examples we can connect with FPGA using write/read operations for /dev/mem file. The second part consists of examples with kernel driver e.g. SPI, GPIO.