The Undocumented Pi

=Hardware=

SoC
There is a nicely ordered table with all BCM2835_registers as found in the GPU code published by Broadcom. Unfortunately, the table does not quite match the SoC in the Raspberry Pi, but it's a good start. The sections below should serve as a companion to that table.

Clocks
All SoC clocks are derived from a crystal oscillator (54.0 MHz for RPi4, 19.2 MHz for all other models). RPi4 has one more oscillator (25.0 MHz), which is used by the VIA VL805 USB 3.0 host controller. A diagram of the clock hierarchy:



Each PLL is a fractional N frequency synthesizer that can generate N/M times the crystal oscillator frequency (XOSC). The integer part of N is controlled by the NDIV field of the  register; the fractional part is stored in. The M refers to the PDIV field of. There is also a prescaler in the feedback path, which is controlled by a bit in the register:


 * bit 11 for PLLH
 * bit 14 for all other PLLs



The loop filter is controlled by three parameters: KA, KI and KP (cf. ). It is most likely some sort of a PID controller, but it is not clear why the first coefficient is called KA and not KD. It may have some significance, though.

A PLL can have up to 4 output channels, each with an independent divider. These PLL channels can be used as clock sources by the individual muxes. There are different kinds of muxes:


 * Oscillator muxes cannot use any PLL channels.
 * Core muxes can use PLL CORE channels.
 * Peripheral muxes can use PLL PER channels.
 * DSIx muxes can use PLL DSIx channels. DSI0 clock source can be taken either from PLLA, or from PLLD, depending on the  bit in the   register.

BCM283x
There is a VCE block to accelerate video encoding/decoding. No documentation AFAIK.

BCM2711
This chip may not have PLLH, or it works differently.

There is no prescaler in the feedback loop. The corresponding bit in ANA1 can still be set, but it does not have any effect on the PLL frequency.

It also lacks the following clock muxes:


 * GNRIC
 * CCP2
 * HSM (controlled through other registers?)
 * SLIM
 * SDC (secondary SDRAM clock)
 * ARM (controlled through other registers?)
 * AVEO

It has the following extra clock mux registers (their names are just made up, because there is no official documentation):

There is a hardware register which contains the chip version and revision (name made up again):

The VCE block was apparently removed, but there is now a HEVC block.

PMIC
The BCM2835 chip has an on-chip SMPS and an LDO for the LPDDR2 memory chip. RPi2 and RPi3 B use custom circuitry to do the power-up sequencing; it is made of discrete components, including an NCP6343 chip (datasheet) at I²C address 0x1c. The RPi 3B+ and RPi 4B boards contain a MaxLinear MxL7704 (datasheet) at address 0x1d.

The PMIC is always on the system I²C bus (I2C8 on RPi4, I2C0 on all other devices).

See also this very informative blog post by James Adams.

=Boot ROM=

=Firmware=

=Abbreviations=


 * CM
 * Clock Manager


 * HSM
 * HDMI State Machine


 * OTP
 * One-Time Programmable (memory)