BeagleBone PRU Notes

The goal of this page is to record information that is pertinent to getting started with the BeagleBone's AM335x Programmable Real-time Unit (PRU).

BeagleBone Programmable Real-time Unit
This is also called the PRU Subsystem (PRUSS) or PRU and Industrial Controller Subsystem (PRU-ICSS). It is optimized to perform embedded tasks that require real-time constraints.

Most important is the purssdrv library to expose functions to the PRU. You can load this library by typing modprobe uio_pruss.

PRU capabilities



 * The PRU has dual 32-bit RISC cores, shared data and instruction memories and an interrupt controller (INTC).
 * 8KB data memory and 8KB instruction memory
 * 12KB shared RAM
 * A small, deterministic instruction set

There is no pipelining done on the processor and there are 29 (r1-r30) registers to use.

Data Sheet is located at http://www.ti.com/lit/pdf/spruh73

Software examples
BeagleBoard/TI has provided example C programs that utilize the PRU on github.

These include: PRU_memAccess_DDR_PRUsharedRAM, PRU_memAccessPRUDataRam, PRU_PRUtoPRUInterrupt, and a PRU assembler.

Full assembly guide is located at http://processors.wiki.ti.com/index.php/PRU_Assembly_Reference_Guide

Instruction Set
Nearly all instructions (with exception of accessing memory external to PRU) are single-cycle execute (5 ns when running at 200 MHz)

Four instruction classes

 * Arithmetic
 * Logical
 * Flow Control
 * Register Load/Store

Instruction Syntax

 * Mnemonic, followed by comma separated parameter list
 * Parameters can be a register, label, immediate value, or constant table entry
 * Example
 * SUB r3, r3, 10
 * Subtracts immediate value 10 (decimal) from the value in r3 and then places the result in r3

Example Assembly
INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR .word 0x48200040/0x48200044 ACTIVEIRQ_MASK .equ 0x7F _IRQ_ISR/_FIQ_ISR: STMFD SP!, {R0-R12, LR} ; Save working registers and the Link register MRS R11, SPSR ; Save the SPSR into R11 LDR R10, INTC_SIR_IRQ_ADDR/INTC_SIR_FIQ_ADDR LDR R10, [R10] ; Get the INTC_SIR_IRQ/INTC_SIR_FIQ register AND R10, R10, #ACTIVEIRQ_MASK ; Apply the mask to get the active IRQ number LDR PC, [PC, R10, lsl #2] ; PC base address points this instruction + 8 NOP ; To index the table by the PC .word IRQ0handler ;For IRQ0 of BANK0 .word IRQ1handler .word IRQ2handler
 * INTC_SIR_IRQ/INTC_SIR_FIQ register address
 * ACTIVEIRQ bit field mask to get only the bit field
 * Save the critical context
 * Get the number of the highest priority active IRQ/FIQ
 * Jump to relevant subroutine handler
 * Table of handler start addresses