BeagleBoard/GSoC/2022 Proposal/TaliaXu

=Proposal for Beaglewire PRU and Support= About Student: Talia Xu Mentors: Michael Welling, Bhilare Proposal:BeagleWire Software

=Proposal=
 * Completed All the requirements listed on the ideas page.
 * The PR request for cross-compilation task: #162.

=Status= This project is currently just a proposal.

About you
Github: taliaxu09 School: [Technical University Delt] Country: The Netherlands Primary language : English Typical work hours: 12PM-8PM European Central Time Previous GSoC participation: This is my first time applying to participate for GSoC. I want to patricipate in GSoC with BeagleBoard because I think this is a great opportunity to gain a deeper knowledge of the code repository of BeagleBoard and explore how to use it together with different peripherals. I also think the BeagleWire could be a promising candidate for some of the topics I wish to look into in my study on visible light communication.

About your project
Project name: RISC-V Based PRU on FPGA and Beglewire Updates

Main Goals:
 * 1) Create RISC-V PRU on BeagleWire
 * 2) Create examples with PRU cores on BeagleWire
 * 3) Improving the stability and implement testbenches for subsystems in standalone cores,
 * 4) Extensive documentation,

Introduction
The BeagleWire is an FPGA cape with the Lattice iCE40HX that can be connected to and interfaced with the BeagleBoard. There are two main goals in this project, the first one is to implement a programmable real-time unit on BeagleWire to allow low-latency I/O control between the main CPU and peripherals. The second one is to revisit and improve the software support for standalone cores, such as the (SDRAM, UART, SPI, PWM).

RISC-V Cores on FPGA
Several open-sourced PRU cores can be leveraged to implement on the BeagleWire

For iCE40:

 * 1) https://github.com/olofk/serv
 * 2) https://github.com/stnolting/neorv32
 * 3) https://github.com/sylefeb/Silice/tree/draft/projects/ice-v

The above cores can be used as a starting point and reference to quickly implement a working RISC-V core on the current BeagleWire cape. Once the cores are able to be run on the BeagleWire, the goal is to focus on the following improvements:
 * 1) Interface between BeagleWire PRU cores and BBB: to create an interface for the BBB to manage both the PRU on the BBB and the PRU on the BeagleWire simultaneously
 * 2) To measure and improve the I/O latency of the PRU cores: to identify any bottlenecks in the implementation of PRU cores for communicating with peripherals and look into ways to improve them if any. The I/O latencites of PRU cores on BBB will be used as a reference.
 * 3) To fit as many PRU cores as possible on the iCE40: to run multiple cores simultaneously on the BeagleWire with shared access to SDRAM. I also plan on looking into the components that are not necessary for BeagleWire to maximize the PRU cores on BeagleWire

For PolarFire:

 * 1) https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fpga

The approach of supporting PRU on PolarFire is less sort out, but the goal is to start with the official support of RISC-V on PolarFire.

Improving the stand-alone cores on BeagleWire
The previous issues on several subsystems of BeagleWire have been addressed with LiteDRAM, but the issues with the standalone cores are left unresolved. As part of my project, I would like to take a further look into the standalone subsystems.