Connect a ARM Microcontroller to a FPGA using its Extended Memory Interface (EMI)

Summary
Although there is the versatile and powerful ZYNQ extensible processor-centric architecture with its on board dual-core Cortex-A9 ARM processor devices, sometimes it is necessary to use a standalone micro-controller in combination with a processor-less FPGA. Of course a standalone micro-controller can also be used in combination with a ZYNQ FPGA.. This note provides a way to hook a FPGA to an of the shelf available ARM micro-controller. The FPGA can use the micro-controller as process controller or as extended multi-peripheral (USB, LCD, Keyboard, and etcetera) device. The micro-controller mostly uses the FPGA as pre-processing high-speed, high performance calculation extension.

Introduction
An FPGA is primary used for computationally intensive, high-speed and/or parallel processing tasks while the ARM micro-controller is widely used due to its versatility, many manufacturers implement it as the core for their applications (Including he ZYNQ family of devices). Because ARM devices are so widely used across the processor sector there is a variation of operating systems available. An application that caused this note to be written was a video application using an FPGA as high speed – parallel video processing engine and a dedicated ARM micro-controller as human interaction interface. The solution provided is to use one Chip Select area of the micro-controllers External Memory Controller (EMC) in SRAM mode and connect this to the FPGA. Figure 1shows the setup of an example video design.

' Figure 1: Micro-controller – FPGA video application. ' The FPGA connects via the External Memory Interface (EMI) to the ARM processor. To prove this concept some design decisions were taken:
 * Use on the market available micro-controller hardware.
 * The Phytec phyCORE-LPC3250 development board was chosen.
 * Use an available Xilinx Development board.
 * Virtex-6 LM605, 7-Series KC705 or VC707 boards.
 * A board with a processor-less FPGA is chosen because the connection between the external processor and FPGA must be proved.
 * A ZYNQ connecting to it's FPGA Block-RAM is topic of another article.
 * Use an OS.
 * The Phytec development system comes with a Linux port.
 * The obvious choice was thus to go for Linux in stead of writing code on the bare metal of the ARM processor.

The Processor
With the choice of the Phytec board came the NXP LPC3250-A9 micro-controller. The Phytec board data can be found on: www.phytec.com. The details of the micro-conroller can be obtained from: www.nxp.com The LPC3220/30/40/50 embedded micro-controllers are designed for low power, high performance applications. NXP achieved these goals using a 90 nano-meter process to implement an ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals.

The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides the virtual memory capabilities needed to support the programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations, and hardware based native Jazelle Java Byte-code execution. The implementation has a 32kB instruction cache and a 32kB data cache. The LPC3220/30/40/50 includes a whole set of peripherals and memory support: The interesting peripheral for this FPGA application is the processors External Memory Interface. The EMI is controlled by the External Memory Controller (EMC), an ARM PrimeCell MultiPort Memory Controller peripheral. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral, Figure2.
 * 256 kB of on-chip static RAM,
 * NAND flash interface,
 * External bus interface (EMI) supporting SDR, DDR SDRAM and static devices.
 * Ethernet MAC
 * LCD controller that supports STN and TFT panels
 * USB 2.0 full-speed interface
 * Seven UARTs
 * Two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces.
 * Two single output PWMs, a motor control PWM
 * Six general purpose timers with capture inputs and compare outputs
 * Secure Digital (SD) interface
 * 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option.

Features of the EMC are:
 * Dynamic memory interface support including Single Data Rate and Double Data Rate SDRAM.
 * Supports mobile SDRAM devices with 1.8 V I/O interface.
 * Asynchronous static memory device support including RAM, ROM, and Flash, with or without asynchronous page mode.
 * 2k, 4k, and 8k row address synchronous memory devices.

links to NXP and Phytec pages

 * Category:NXP
 * Category:Phytec