image/svg+xml
PLLchannels
PLLA
DSI0
CCP2
CORE
PER
PLLB
ARM
PLLC
CORE0
CORE1
CORE2
PER
PLLD
DSI0
DSI1
CORE
PER
PLLH
PIX
AUX
RCAL
XOSC
peripheralmuxes
coremuxes
oscillatormuxes
PLLs
dsi0muxes
dsi1muxes
generatedclocks
TD0
TD1
clockmuxes
TIMER
PULSE
OTP
TEC
TSENS
SDC
H264
ISP
V3D
VPU
HSM
UART
VEC
SLIM
GP0
GP1
GP2
DPI
DFT
SMI
CAM0
CAM1
AVEO
PCM
PWM
EMMC
DSI0E
DSI0P
DSI1E
DSI1P
0
1
2
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
0
1
2
3
4