Difference between revisions of "ARM926EJ-S"
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The ARM926EJ-STM fully synthesizable processor features a Jazelle technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces, memory management unit (MMU). It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for Multi-layer AHB based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution. | The ARM926EJ-STM fully synthesizable processor features a Jazelle technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces, memory management unit (MMU). It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for Multi-layer AHB based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution. | ||
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| − | Applications | + | === Applications === |
| + | * Next generation smart phones, communicators & PDA's | ||
| + | * 3G baseband and applications processor | ||
| + | * Platform OS based devices | ||
| + | * Digital still camera | ||
| + | * Audio and video decoding | ||
| + | * Automotive infotainment | ||
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| − | Features | + | === Features === |
| + | * 32/16-bit RISC architecture (ARMv5TEJ) | ||
| + | * 32-bit ARM instruction set for maximum performance and flexibility | ||
| + | * 16-bit Thumb instruction set for increased code density | ||
| + | * DSP instruction extensions and single cycle MAC | ||
| + | * ARM Jazelle technology | ||
| + | * MMU which supports operating systems including Symbian OS, Windows CE, Linux | ||
| + | * Flexible instruction and data cache sizes | ||
| + | * Instruction and data TCM interfaces with wait state support | ||
| + | * EmbeddedICE-RT logic for real-time debug | ||
| + | * Industry standard AMBA bus AHB interfaces | ||
| + | * ETM interface for Real-time trace capability with ETM9 | ||
| + | * Optional MOVE Coprocessor delivers video encoding performance | ||
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| − | + | [http://www.arm.com Arm Ltd Web Site] | |
| − | + | [[Category:ARM processors]] | |
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Latest revision as of 12:23, 10 February 2008
The ARM926EJ-STM fully synthesizable processor features a Jazelle technology enhanced 32-bit RISC CPU, flexible size instruction and data caches, tightly coupled memory (TCM) interfaces, memory management unit (MMU). It also provides separate instruction and data AMBA AHBTM interfaces particularly suitable for Multi-layer AHB based systems. The ARM926EJ-S processor implements the ARMv5TEJ instruction set and includes an enhanced 16 x 32-bit multiplier, capable of single cycle MAC operations. The ARMv5TEJ instruction set includes 16-bit fixed point DSP instructions to enhance performance of many signal processing algorithms and applications as well as supporting Thumb and Java bytecode execution.
A hardened implementation of the ARM926EJ is now available from the ARM Processor Foundry Program and the DesignStart Program
Applications
- Next generation smart phones, communicators & PDA's
- 3G baseband and applications processor
- Platform OS based devices
- Digital still camera
- Audio and video decoding
- Automotive infotainment
Features
- 32/16-bit RISC architecture (ARMv5TEJ)
- 32-bit ARM instruction set for maximum performance and flexibility
- 16-bit Thumb instruction set for increased code density
- DSP instruction extensions and single cycle MAC
- ARM Jazelle technology
- MMU which supports operating systems including Symbian OS, Windows CE, Linux
- Flexible instruction and data cache sizes
- Instruction and data TCM interfaces with wait state support
- EmbeddedICE-RT logic for real-time debug
- Industry standard AMBA bus AHB interfaces
- ETM interface for Real-time trace capability with ETM9
- Optional MOVE Coprocessor delivers video encoding performance
