Difference between revisions of "ARM Processor"
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| + | NOTE: increased pipeline length reduces the amount of work done at each stage in the pipeline, therefor enabling high operating frequencies and performance. however as the pipeline length increases, system latency also increase due to increased number of clock cycles to fill the pipeline before an instruction can be executed. | ||
Revision as of 12:34, 6 November 2007
| CPU Core | MMU/MPU | ISA |
|---|---|---|
| StrongArm | MMU | v4 |
| ARM7TDMI | none | v4T |
| ARM7EJ-S | none | v5TEJ |
| ARM720T | MMU | v4T |
| ARM920T | MMU | v4T |
| ARM922T | MMU | v4T |
| ARM926EJ-S | MMU | v5TEJ |
| ARM940T | MPU | v4T |
| XScale | MPU | v5TE |
| ARM946E-S | MPU | v5TE |
| ARM966E-S | none | v5TE |
| ARM1020E | MMU | v5TE |
| ARM1022E | MMU | v5TE |
| ARM1026EJ-S | MMU+MPU | v5TE |
| ARM1136J-S | MMU | v6 |
| ARM1136JF-S | MMU | v6 |
| CPU Core | Pipeline Depth | Typical MHz |
|---|---|---|
| ARM7 | 3 stage | 80 |
| StrongArm | 5 stage | 133 |
| ARM9 | 5 stage | 150 |
| ARM10 | 6 stage | 260 |
| XScale | 8 stage | 400 |
| ARM11 | 8 stage | 335 |
NOTE: increased pipeline length reduces the amount of work done at each stage in the pipeline, therefor enabling high operating frequencies and performance. however as the pipeline length increases, system latency also increase due to increased number of clock cycles to fill the pipeline before an instruction can be executed.
