Difference between revisions of "BCM2835 datasheet errata"
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== p38 typo ==
== p38 typo ==
Revision as of 02:16, 31 March 2012
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BCM 2835 datasheet errata
The (partial) datasheet was published here: http://dmkenr5gtnd8f.cloudfront.net/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
It has a couple of typos. Some more serious than others.
Let's gather those datasheet typos and errors here.
The quality of the datasheet is high. It looks like it contains the information that programmers need.
It also "does the right thing" with reserved bits. Many datasheets specify "write: don't care, read as zeroes". Broadcom specifies the reserved bits the other way around: "Write zeroes, read: don't care".
This is the correct way to do it. If you expand the hardware the hardware may be enhanced and do "different things" if you write ones to the previously "reserved" bits. If you follow the datasheet, and write zeroes as specified to the reserved bits, the hardware guys can make sure you're not going to run into surprises. And by specifying "read: don't care" you can allow future hardware to provide status bits there.
Switch on option for linking, so cross-references and table of contents can be jumped through.
p7 footnote typo
precuations should be precautions.
The table on page 25 has the bit numbers wrong. Some bits are mentioned twice, some not at all.
I'm guessing it should be something like:
|31:24||TX FIFO level||The number of data units in the transmit data FIFO||R/W||0|
|23:16||RX FIFO level||The number of data units in the receive data FIFO.||R/W||0|
|15:10||-||Reserved, write zero, read as don’t care||R/W||0|
|9||TX Full||If 1 the transmit FIFO is full
If 0 the transmit FIFO can accept at least 1 data unit.
|8||TX Empty||If 1 the transmit FIFO is empty R/W 0
If 0 the transmit FIFO holds at least 1 data unit.
|7||RX Empty||If 1 the receiver FIFO is empty R/W 0
If 0 the receiver FIFO holds at least 1 data unit.
|6||Busy||Indicates the module is busy transferring data.||R/W||0|
|5:0||Bit count||The number of bits still to be processed. Starts with 'shift-length' and counts down.||R/W||0|
I strongly suspect that the CDIV counter is only 14 bits wide. The bottom bit doesn't work as per specifications, and because the "0" results in 32768, the top bit doesn't either. An easy implementation would implement the 0 value as the maximum divisor. Not as "half the maximum".
Another option is that SCL = cor clock * 2 / CDIV and that the counter is 15 bits after all. (only the lowest bit missing).
harware instead of hardware (second paragraph)
The table, legend for table 6-31, started on page 103 shows in red: TXD0, RXD0, CTS0, RTS0 which should be TXD1, RXD1, CTS1, RTS1.
top line: device should be devise.
The registers base addresses -> the registers' base address or The base address of the registers is 0x7e21_4000.
The last entry of section 15.1.
The entries in the table should specify the choice that Broadcom made when instantiating the USB controller IP from Synopsys.
Possibly the "choice" hasn't been specified. Or maybe the "0=32, 1..5=512, 6,7=768" is the option that was chosen?